Other Parts Discussed in Thread: UCC28019
In the thread I referenced, the gate waveforms from the IC, on time is coming out to be maxed out.
As per the explanation mentioned in the thread:
"If you notice, your COMP voltage is maxed out (in fact, it is exceeding the 7V AbsMax spec!). Your gate on-time is maxed out and VSENSE is on the high end. The PFC has likely hit it's OCP level and you are peak-regulating (√2 * 230Vac + Vdiode = 326V)."
What might be causing the Vcomp to exceed and thus leading the gate on time to be maxed out here?
Also, what does "Vsense(4.1V) is on the high end" mean when its typically referenced value is for 5V?