Our design has 5 voltage rails that are connected to the SENSEx inputs on two TPS38600 devices - V1 (SENSE1-1), V2 (SENSE1-2), V3 (SENSE1-3) and V4 (SENSE1-4) on device 1 and V5 (SENSE2-1) on device 2. Note that VDD of both devices is V4. These rails are connected to the SENSEx inputs through voltage dividers that equate to approximately 0.410 volts when each rail is in regulation. This 0.410V exceeds the SENSEx threshold (VIT- of 0.4V +/- 4mV) which causes the devices to kick off the delay timer. Once the delay timer has expired, the device releases the POR output and the signal goes HIGH via a pull-up resistor. We’ve programmed the timer to be 90.5 ms per the equation in the datasheet which equates to a CTn capacitance of 0.022 uF (22 nF) for each input.
Our understanding is that there are two conditions required for the 90.5 ms programmable timer to start. In addition to the SENSEx input exceeding VIT-, VDD also needs to exceed 0.9V. All 5 *RESET outputs are wire OR’d together so the POR is not released until the last timer has expired.
There are two issues we've encountered. 1. Every rail's CTn input starts to ramp up almost immediately when VIT- > 0.4V and VDD > 0.9V except for V2 which is way off and looks to be started about 60 ms later than expected. Also, all of the CTn ramps from 0V to 1.24V are approximately 120 ms and not 90 ms as I would expect based on the capacitance value chosen. I thought maybe the parasitic capacitance on the board would be contributing but we measured using an LCR meter and it was in the pF range. If we make several assumptions such as the capacitance being on the high side (1% tolerance), the CTn current being on the low side (235 nA), and the CTn threshold being on the high side (1.299V) then the actual hardware just barely meets the calculations in the datasheet. However it seems unlikely the device would be operating at the limits in all the aforementioned parameters. Any thoughts?
