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BQ25713B: CHRG_OK pin not HIGH although the voltage of VBUS is around 4.9V

Vu Dien
Prodigy 10 points
Part Number: BQ25713B
Other Parts Discussed in Thread: BQ25713,

Hi,

I have a problem in charging with BQ25713/BQ25713B when The pin CHRG_OK doenn't HIGH although VBUS is aroung 4.9V. In datasheet, When any fault occurs, CHRG_OK is asserted
LOW. what is possible fault in this case?

 I also observed that in the initial VBUS was at 4.9V, the CHRG_OK was HIGH until the nCHARGER_ILIM_HIZ pin was HIGH, CHRG_OK was LOW as an attachment. 

Best Regards,

Dien Vu

  • +1
    TI__Expert 4780 points

    Hello Dien,

    It looks like the CHRG_OK low is asserted when VSYS hits 5.1V. If the charger is set up as 1S, then the SYS OVP is 5.1V, so SYS OVP condition is probably what's triggering the CHRG_OK to go low.

    When ILIM_HIZ is low, the device is in HI_Z mode, when you force ILIM_HIZ high you are taking the device out of HIZ mode, and the device starts regulating VSYS. Something in your hardware setup is causing VSYS to hit the OVP condition.

    Please check your configuration on all the pins against the datasheet recommendations. You can also use the EVM schematic as a reference (BQ25713EVM).

    Thanks,

    Khalid

  • 0 in reply to Khalid Bairuti
    Prodigy 10 points

    Thanks Khalid,

    I have checked SYSOVP fault bit REG0x20[4] and it's high. 

    The problem is my device used to work well with configuration on all the pins as the datasheet recommendations. maybe something broke in my device.

    Do you know which configuration pins when it break that lead SYSOVP happen or Do you have any asumptions?

    Thank you very much

    Dien

  • 0 in reply to Vu Dien
    TI__Expert 4780 points

    Hello Dien,

    I would recommend to check all your MOSFETs and Inductor for any shorts. You could be shorting input directly to output. Also confirm the voltage on CELL_BATPRESZ pin is as expected for the target cell count you are using.

    Khalid

  • 0 in reply to Khalid Bairuti
    Prodigy 10 points

    Hi ,

    What is actually output behaviour of LODRV1/HIDRV1  and LODRV2/HIDRV2 pins? Here is what I measured these pins at the moment SYSOVP happen:

    LO/HI-DRV2LO/HI-DRV1

    Is this correct behaviour? or because HIDRV1 and HIDRV2 get HIGH that make shorts happen?

    Thanks,

    Dien

  • +1 in reply to Vu Dien
    TI__Expert 4780 points

    Dien,

    HIDRV1/LODRV1 and HIDRV2/LODRV2 are the FET gate drivers. They will go High/Low to switch the High Side and Low Side FETs when switching begins, to regulate VSYS. It appears that as soon as switching starts you are getting a SYSOVP condition. It looks like the VSYS is following the HS drivers exactly, which could indicate a short from HIDRV1/2 to SYS.

    Khalid