UCD90320: Behavior check for UCD90320

Hi Yihe:

1. How long will LGPO take when logic of it is changed?

2. What status of LGPO during logic of it is chagned?

Hi Yihe:

1. While UCD90320 is boot-up and initialization, no matter GPIs are set as active high or low, they're all high impedance right?

2. While UCD90320 is boot-up and initialization, what status & impedance will following condition have?

(a) GPOs are set as output high

(b) GPOs are set as output low

(c) LGPOs are set as output high

(d) LGPOs are set as output low

3. After UCD90320 finished bootup and initialization, what status & impedance will above condition have?

Hi Yihe:

*PCIE_CLK_SEL is LGPO with logic "invert of PCIE_MFG".

*There're two voltage dividers with same value and Rupper is connected to P3V3. PCIE_CLK_SEL is connected between these two voltage dividers.

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As first diagram shows, UCD90320 on my board took around 55ms for initialization.

But if we zoom in, as 2nd diagram shows, it'll be low for around 380us.

Is this a correct timeline?