We are trying to bring down the Transient response curve to within 100mV but we unable to achive.
Could you please suggest the right method?
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You can customize the load transient specs through Webench as shown below. Once you click "redesign" it will design your components to meet that specification.
I have also created a design that fits your desired transient pk-pk<100mV accessible here: https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=E8D463E86A5F9111
For the results below, compensation and Cout were modified from your original design to reduce pk-pk.
Thanks for your immediate support.
We tried this settings and noted out waveforms attached here.
Just wanted to confirm this point. We got the steady state ripple <6mv in DC-DC.
Please confirm the whether we are getting correct values or not?
How much % difference can expect in the Actual Testing vs simulation?
I run it from my side i did not see the start up issue.
We provided the PSPICE models on the product folder of this device, i recommend running some SIM with that to tune your design.
Typically Simulation is good starting point for any design to give guidelines on the SCH to achieve your design goals, but evetualy has to be tested and tuned further on the bench