Other Parts Discussed in Thread: TIDA-01573, LMG1020
I want to drive LD SPL TL90AT08 (IF = 40 A; tp = 100 ns; D = 0.01 %, Vop=11V) with an avalanche transistor. I need to produce trains of 100 nc square pulses with 1000 ns delay after each pulse, n= 100 pulses followed by 10 ms delay after the train is delivered. Osram recommends to use BSP318S FET but it looks like it can deliver max 30A so I want to try EPC2019. Considering operating frequency of 1 Mz and 100nc pulse I suppose I should not expect any significant RF issues and I’d like to attempt to drive 3 LDs connected in series. As I have no experience working with nc pulses and Mz frequencies I'd like to test the idea with TIDA-01573 board. I’ve got a number of questions:
1.The spec for the board frequency range: 0.1Mz-1Mz. I understand the upper limit but I can’t comprehend why there is a low limit . As my trains are run with 100Hz frequency the board should not work. Is it correct?
2.Will the buffer shorten any pulse to 1 nc duration? If it does can I bypass it?
3. Why 4 X 0.1 uf caps are used instead of 1 0.4uf? I would have to replace caps on the board to get longer pulses. How do I calculate caps value for 100nc pulse?
4. The only issue that I can see with 3 LDs is that the pulses get longer and more triangle like. I don’t see any other problems in the 3X impedance increase (from my experience LDs considered a resistive load so additional capacitance will come from leads) if anything it should help with ringing which seems to me has a high probability to occur in this circuit. Are there others?