UCC28019A: Design help

Hi Gautham,

Thank you for the query on UCC28019.

I think you want to use UCC28019 for a DC-DC application with input voltage-80/125V and output voltage 390/410V.  It can be used in this application and will generally function.  The only issue that I see would be the bandwidth of the voltage amplifier.  Because this device was defined, and designed, for PFC applications, and PFC circuits have to be slow, the internal volatage amplifier was assumed to operate with a very low crossover frequency (less than 20Hz).  I honestly don't know what the limitation would be for an application that required much more bandwidth like in your case.  The design calculator will not reliably calculate the compensation values for the voltage loop as it limits the bandwidth. Please let us know if you have any questions.

Regards,

Harish

Hi Harish,

Thanks for getting back. I understand the limitation. Could you recommend another controller/topology that I can use instead?

Regards,

Gautham venkat

Also, Equations that involve frequency, like the calculation of the output cap would not be applicable, right? Would I instead calculate it as we do normally as this? 

Hi Gautham,

I have seen a number of customers use UCC28180 / UCC28070 for DC-DC applications. But again there is no ready reference design with these too.

Cout capacitor is designed accounting for line drops and the allowable voltage DC bus drop under such conditions. If you are not designing for such conditions normal boost converter equations should apply as you mentioned.

Thank you

Regards,

Harish

Hi Harish,

Thank you for the clarification. Going back to the topic of compensation, I cant seem to get the values of Rvcomp and Cvcomp_p right. How can I approach this?

Hi Gautham,

Thank you for reaching out. 

I feel there are some issues with the way loop crossover is set. The zero from the compensator is set using RCOMP/CVCOMP to deal with the low frequency pole due to pulse width modulator to power stage. Your high frequency pole is placed 50hz and PWM stage pole is 103hz and cross over is set at 20hz. So your compensation designer for voltage loop is not setup properly in terms of crossover frequency/pole/zero locations. Kindly follow the datasheet procedure to arrive at approximate values.

Please let us know if you have any questions. 

Regards,

Harish

Hi Harish,

That helped, Thanks!

I have another question now, How would I go about designing an Input filter for this setup, given I don't use a Bridge diode?

Regards,

Gautham

Hi Gautham,

Thank you for the reply.

I would honestly tell there are going to be a lot of design iterations here depending on the layout/ actual measurements and it is going to be difficult to suggest values. For a quick start for your design, I would suggest using the recommended values from EVMs/ any PMP reference design of approximate power level which you intend to design. You can choose to not populate/change them during your actual testing.

The following are two app notes on the design guideline for emi filter:

https://www.ti.com/lit/an/snva489c/snva489c.pdf

https://www.ti.com/lit/an/snva538/snva538.pdf

Please let us know if you have any additional questions.

Regards,

Harish