This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS548B27: Output Voltage Ripple Reduction

Part Number: TPS548B27
Other Parts Discussed in Thread: TPS54J061, TPS548A28

I am trying to reduce the output voltage ripple on our TPS548B27 design.

According to the datasheet, with VIN = 4.5 – 5.5V, IOUT = 2.5A, VOUT = 1.03V, and fSW = 800 kHz, the inductor should be:

LMIN = 1.046 uH

LMAX = 2.790 uH

Yet, Webench(R) Power Designer chooses 174.398 nH for the inductor for these same input parameters. This causes the inductor ripple current to be 6A, when IOUT is only 2.5A. This results in a negative ILIM_VALLEY calculation.

Currently, our design is using a 330nH inductor and 366.8uF of output capacitance. This results in too much output voltage ripple.

I would like help in understanding what I need to change in order to reduce the output voltage ripple of this power supply.

Regards,

Jeff K

  • Also, with the limited input voltage range, the low output current and voltage, does this design still need to meet 50mV transient per 10A step? This restriction makes the output capacitor selection impossible.

  • Most 2.5A applications would have use TPS54J061 (6A).   It has the same control scheme, smaller and similar features as TPS548B27.

    Webench sets the ripple current to 6A which is ~0.3 of 20A.     

    The ripple current can be lowered to 3A in webench which is still high for a 2.5A application

    or you can use an excel sheet located here https://www.ti.com/lit/zip/slvrbh6

    I do not understand the 50mV 10A step comment

     The transient requirements are set by the load.     The loads slew rate can be fast such as 10A/us or significantly less. 

    Using a higher switching frequency, higher inductance and higher output capacitance  are ways to lower the output ripple.

    An inductor  in the range of 1uH to 2.2uH  is most suitable for a 2.5A requirement.   

  • I understand that the datasheet and Webench sets the inductor current to 30% of Iout. In my 2.5A design, this would want the inductor ripple current to be 750mA. What I don't understand is why does the Webench select an inductor that falls outside the 15-40% recommendation on inductor ripple current? The datasheet equations show my inductor should be 1.046 - 2.790 uH, but Webench selects 174.398 nH, which is equivalent to 65% of Iout for inductor ripple current. It seems like an error in the algorithm.

    The Istep and Vripple question is about the datasheet and how is 10A and 50mV, respectively, defined. I didn't see in the documentation where these numbers are determined. In a 20A system, I can see testing the transient response for a change in Iout of 50%, thus 10A and the 50mV might be a percentage of Vout (1V) or 5% change in Vout due to 50% change in Iout.  If that is the case, then I can scale these numbers accordingly to determine  Cout_undershoot and Cout_overshoot values.

     Is there any possibility of eliminating or reducing the large 60mVpp spikes that occur at the switching frequency or is this an inherent artifact of the D-CAP3 control architecture?  I am using FCCM @ 800kHz in this design. This power supply is used to drive an FPGA that specifies 1.03V +/- 30mV and thus the power supply needs to have much lower Vout ripple. Here again is the picture of the 1.03V Vout showing the 60mV spikes at the 800kHz switching frequency.

  • The 60mV spikes are HF ripple from the switching in the power stage and can be reduced by following some of 

    the techniques in https://www.ti.com/lit/ml/slyp709/slyp709.pdf particularly on  pg 25 to 28.

    The whole document has some useful information regarding the causes, measurement and reduction of noise and ripple.

    The 8-9 mV ripple is a function of the input voltage, output voltage, switching frequency, inductance, and output capacitance and within the +/-30mV.

    Assuming a pcb layout is optimal, the next step would be to use high frequency capacitors in parallel reduce the spikes.   

    The webench should work similar to the TPS548A28 webench and use the Iout as a parameter.  But even on the TPS548A28 at the low output current, the ripple current is fixed to be greater than 1.5A.  Webench assumes a developer is using an output current greater than 20% of rated current.

    The excel sheet will give some flexibility on selecting components. 

    The 10A step and the 5% is typically requirement for a rail on a processor and was used as an example.

    Figure 6-11 and 6-12 show the loop response. 

    Typically we get a power supply specification that reads 

    Vout =  TBD V

    DC + AC Tol = +/- TBD %

    Iout = TBD A

    Iout step = TBD A to TBD A    with TBD A/us slew rate.

    The above specifications are used to make output filter selection.  The DCAP3 control is good for fast transient response.   In figure 6.11, the converter switches faster during the load step up to minimize the droop and conversely during unload skips switching to minimize overshoot.

    If the max output current is 2.5A, i would expect load step to be less than 2.5A.