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LM5035CEVAL: Duty cycle problem of LM5035C

jeno.zhang
Expert 2525 points
Part Number: LM5035CEVAL

Hello,

The duty cycle of LM5035CEVAL is relatively high under light load (about 35%)， Please help analyze the cause， Thanks！

  • 0
    TI__Mastermind 28015 points

    Hi and thanks for posting to E2E - What is the duty cycle you are expecting? Please provide waveforms, schematic or description of input voltage, output voltage, frequency, topology, transformer turns ratio? The more information you can provide, the better TI is able to support you. You should also consider using TI Power Stage Designer as a way to verify theoretical duty cycle for any power stage. Power Stage Designer allows top level sim for most popular power topologies.

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    Expert 2525 points

    Hello，

    The customer uses TI's evaluation board, the model is LM5035CEVAL, which is not a product developed by the customer;

    Problem description:

    1. When there is no load, the MOS drive duty cycle of the bridge arm is large. When the 36V voltage is input, it is about 35%. How is this achieved?

    2. The drive dead time of bridge arms Q11 and Q12 is about 100ns. How to avoid common conduction?

    3. How can C3-C6 capacitance be obtained? Is there a calculation method for transformer output inductance?

  • 0 in reply to jeno.zhang
    TI__Mastermind 28015 points

    Hi

    1. When there is no load, the MOS drive duty cycle of the bridge arm is large. When the 36V voltage is input, it is about 35%. How is this achieved?
      1. You are comparing no load duty cycle to 36V input duty cycle? What is the voltage at no load? What is the load at 36V when D=35%? Please compare apples-to apples and even better if you can include waveforms describing input, output voltage current and duty? 
    2. The drive dead time of bridge arms Q11 and Q12 is about 100ns. How to avoid common conduction?
      1. Dead-time is internally fixed at 45ns<Td<100ns and is specified in the data sheet under "Main Output Drivers (HO and LO Pins)"
    3. How can C3-C6 capacitance be obtained? Is there a calculation method for transformer output inductance?
      1. C3-C6 are input capacitors. Since the full-bridge is a buck derived topology, it has a pulsed AC input current. The input capacitors are determined the same as with any buck topology and are sized for a desired input voltage ripple and maximum RMS input current at low input voltage, maximum load. TI Power Stage Designer can help with the capacitor calculations.

    Regards,

    Steve M