Dear TI team,
Good evening.
We have designed LM26480 according TI reference and webench design for FPGA power supplies.
As I said we have connected Buck and LDO outputs from LM26480 to FPGA.
We have given delay between two LDO outputs,as per switching delay needed for FPGA.
The delay has been achieved through RC network connected to enable signals of those LDOs of LM26480.
In simulation environment by connecting load and without actually connecting specific FPGA,we are able to see delay in LDO outputs.
But in practical scenario(When connected with FPGA),we are not getting delay in LDO.
We would like to share schematic and verify.
Kindly reply.
Thank you,
Girish Kantharaju
