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Hi Matt,
You mean the TI version of MC78M12CDTRKG refers to the App note, correct? I did not find any link to the TI app note on the PDF document from On Semi.
We refer to the App note: "Semiconductor and IC Package Thermal Metrics" to make reference of how we measure our Thermal Metrics. Furthermore, TI follows the JEDEC standards, therefore, we use High-K 2s2p unless otherwise specified.
Having said that, there is another app note that talks more about some of the dimensions we use.
"Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs"
In addition to this, the copper pattern is signal layers with 2oz on top and bottom and two solid copper planes of 1oz for internal planes.
Furthermore, when we look in the Data Sheet for LM78M Section 9.2.3 there are some curves that show the impact of copper area for theta ja
Also, section 11.1.1 Thermal Considerations shows that theta ja is an application variable.
You can also refer to this other app note: AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) (ti.com).
Best,
Edgar Acosta
Sorry edgar, I grabbed the Onsemi PN from my comparison table rather than the TI PN. The subject line should be changed to reference TI PN UA78M12CKVURG3. I didn't see any application curves in the document. I need to make sure I am comparing apples to apples regarding theta JA.
Hi Matt,
I apologize for the mismatch, the LM78 is also an alternative device for the Onsemi device:
With the exception of the application curves shown in the LM78 datasheet, all the previously shared information applies to all TI devices.
JEDEC standards is something everyone in the industry uses, therefore, we reference to the app note which essentially reports how the Rja are measured due to the JEDEC standards by using a High-K 2s2p configuration.
Lastly, the Rja will vary depending on die size and PCB layout design and copper thickness. Again, what we show in our DS is following JEDEC standards.
Best,
Edgar Acosta
Hmmm. After sleeping on this I am thinking I need to be looking at "Junction-to-case (bottom) thermal resistance" instead so that we take out the PCB variable altogether.
Correct me if I'm wrong but if TI has published an equal or lower Theta JC(bottom) and the case bottom dimensions are identical, then the thermal characteristics are as good or better, right?
Problem is that the UA78M12CKVURG3 datasheet does not list that parameter. Is that hidden somewhere in internal documentation or do they have to get a test engineer to do the test?
Hi Matt,
Theta JC also has some board dependency.
uA78 is one of our older devices and inherited from National Semi, and the Thermal Information table should be updated. I can run this by our Thermal Group to get updated JEDEC values, but this will take some time.
Lastly, we tend to use more the Ψ metrics when we do some of the measurements in the Lab:
However, these are not shown in the ua78 DS.
I highly recommend looking into the TPS7B88-Q1 as it is one of our newer devices:
You will see that some of the Thermal Metrics numbers are quite similar for the KVU package, as an example here is TPS7B81-Q1:
They are not the same because die size can differ and notice that this is a 5 pin device compared to a 3 pin KVU.
Also, we also have the following app notes that can help further understand more about Thermals.
How to Evaluate Junction Temperature Properly with Thermal Metrics (Rev. B)
Using Thermal Calculation Tools for Analog Components (Rev. A)
An empirical analysis of the impact of board layout on LDO thermal performance (ti.com)
Best,
Edgar Acosta