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BQ24253: Reference or Document for detect and setting method of EN1/EN2 and external MCU

Guru 19575 points
Part Number: BQ24253

About datasheet page 23, I think that EN1 and EN2 should set from D+ and D- detection (Ex, detect CDP →1.5A, SDP →0.5A).

Is there any document or reference design for setting method about external MCU?

Please refer need information below;

・Way to MCU detect for inserting USB

・Way to MCU obtain the decision of D+/D-, and choice to set EN1/EN2: High or Low.  

Best regards,

Satoshi

  • HI Satoshi,

    There is no document. /PG goes low when D+/D- is complete.  The EN1 and EN2 do not take effect until D+/D- detection routine is over and a change on the status of the EN1 and EN2 occurred.  I recommend ending with EN2 = 0 and EN1=1 so that the ILIM and VDPM resistors control input current limit and VDPM but that means one or both of the pins must be set to something other than those values at some point before the final setting, i.e. one or both have to change status after D+/D- completes.

    Regards,

    Jeff  

  • Hi Jeff 

    Thank you for reply,

    Are EN1 and EN2 need to set after D+/D- status complete?

    For set EN1 and EN2, is there way to MCU monitoring the charge status from D+/D-?

    Best regards,

    Satoshi

  • Hi Satohsi,

    Yes, one or both ENx must change after D+/D- complete.

    No, D+/D- is only used to set input current limit after startup.

    Regards,

    Jeff

  • Hi Jeff

    Thank you for reply,

    When MCU can't monitor D+/D-, it can't monitor the USB compatible (CDP or SDP) and can't judge and change EN1/EN2 status.

    Is there any way to monitor the USB compatible?

    (Or, it is the best that automatically change the current limit)

    Best regards,

    Satoshi

  • Satoshi,

    The USB BC1.2 spec says for the MCU to enumerate with the USB host after detection and then change the input current limit if enumeration finds that higher current is available. If the MCU can't do this, then the only way is for the MCU to always change the ENx lines or possibly add a NFET with gate tied to /PG, source at GND and drain at EN2 that pulls EN2 to 0.

    Regards,

    Jeff