Dears,
Cold you help to review the sch, the Q1 VDS peak voltage is 180V, abnormal.
Dear Sir/Madam,
The the primacy side FET off voltage should be Vin + N_pri/N_sec * Vout. N_pri/N_sec + V_overshoot is 4 for JA4387-AL, if your Vin is about 50 V, the total off voltage except the V_overshoot should be ~98 V which is close to you waveform.
For V_overshoot caused by energy stored in stray inductance, you could reduce it by adjusting the snubber circuit or increasing turn off time. You can try to short the D12 and do not solder Q2 to make the swathing off slower.
Best regards,
Diang
Hi Sir/Madam,
Thanks for your updates!
The root cause of this voltage overshoot normally is the stray/leakage/other inductance and device's output capacitance (Coss) oscillation.
1. Further increase the gate resistor to 30 Ohm.
2. Reduce R9 resistance, and you may need to increase the power rating for it.
3. Try to short L4 since the voltage ringing at C22 and C14 could be coupled to the Coss of the MOSFET.
Updated on Jan/17/2023: It has been a relatively long period that we have not received your reply. I will close this thread for now. Please open a new thread if you have further questions.
Best regards,
Diang
