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TPS51116: Power management forum

Part Number: TPS51116
Other Parts Discussed in Thread: CSD87330Q3D, TINA-TI,

Hello TI Team,

I have used TI component "TPS51116RGET" in my design for DDR3L power requirement along with TI's MOSFET "CSD87330Q3D". 

But I have been trying to simulate the same design for last 2 weeks and observed following issues-

With Cadence PSpice: - It showed some error and I couldn't resolve them (even tried with un-encrypted PSpice model) . Here I have attached recent error in PSpice


After this, I tried with TINA-TI. On TINA tool, I got VDDQ output voltage (around 1.35V) and VTTREF (around 0.675V). But VTT is coming completely out of range (below 0.5V). 

I got above results on following operating conditions-

Vin= 5V

Load resistor @ VDDQ (SYS_1V35) => 1 OHM   (1.35A)

Load resistor @ VTT (SYS_1V35) =>  225 mOHM   (3A)

Load resistor @ VTTREF (SYS_1V35) => 67.5 OHM  (10mA)

Please see the attached circuit diagram that was used for the simulation- 

Please see the attached simulation results of the above circuit using TINA-TI-


I tried with NO LOAD condition also and  got following results- 


Then, I tried in S5 mode also (S5== 5V and S3== 0V) and got following results- 


For the reference please find attached my Schematic design (SCHEMATIC1_DDR3L.pdf) of this component- 


Please help me out with this so that I can verify the Output Voltage Ripple. 

Kindly Review my attached Schematic (SCHEMATIC1_DDR3L.pdf).

Thanks & Regards

Raj Kumar

  • Hello,

    It seems there is oscillation at 10KHz. Are the output capacitors pure ceramic with no ESR? You may add 50 mOhms in series with the 100uF output capacitors and try. First want to make sure the TINA model is working correctly.


  • Hello, 

    Thank you so much the response. 

    I have tried with 50mOhm series register also But I couldn't see the output results because TINA-TI tool is showing some error. please see the attached error's screenshot- 

    Thank You

    Raj Kumar

  • Hi

    Mahmoud will help you when he is back to office.



  • Hi Yihe,

    Greetings of the day and Thanks for the update!

    I will be awaiting for his (Mahmoud) response on this. 

    by the time he (Mahmoud) comes, I want to add that I have already completed the schematic design and placement. but unreliable simulation results are making me feel under confident on this. So, I Request you to please get REVIEWED attached my Schematic as soon as possible.

    Here, I am attaching my schematic.  


    My operating conditions are as follow-

    Vin- 5V, Vout- 1.35V,

    Iout(Vddq)- 1.3A

    Iout(Vtt)- 2A

    Iout(Vtt_ref)- 10mA

    Application Mode- Current Mode

    Current Sensing Scheme- Rds(on) sensing scheme.

    Please let me know if you need any other information about it. 

    Thank You

    Raj Kumar

  • Hi

    Thank you for the details and he will get back to next week



  • Hello Raj,

    I'm not sure what is wrong with TINA model. I reviewed the schematic and looks OK. I recommend to add a 10 Ohm resistor between SYS_1V35 and R1372. The added resistor is for measuring the loop.

    Please close the thread as resolved if your question is answered and let me know for further support.


  • Hello Mahmoud,

    Thanks for the response. 

    As it's simulation is Not running so I have to theoretically verify the circuit. 

    While going through the below paragraph- 

    ""  Choose output capacitance

    When organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP) are used, ESR to achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The peak-to-peak ripple value can be estimated by ESR times the induct or ripple current for stable state, or ESR times the load current step for a fast transient load response. When ceramic capacitor(s) are used, the ESR is usually small enough to meet ripple requirement. In contrast, transient undershoot and overshoot driven by output capacitance becomes the key factor in determining the capacitor(s) required.""

    I came to know that I have to intentionally choose the Output Capacitor such a way that It could give some Ripple at output. 

    But I think- 

    1) Ripple at output is undesirable.

    2) ESR should be minimal.  

    But Here in datasheet, it is recommended to Keep quite more ESR to produce the Ripples. Am I rightly understood? please verify. 

    If YES then Kindly suggest me How would I decide the ESR & Capacitor Value for my operating conditions Because In datasheet I couldn't find any Formula or Procedure for the same. 

    for D-Cap mode, It is given i.e. shown in below paragraph but NOT given for Current Mode. 

    ""  Choose the Components

    Refer to the instructions in the current mode design example to choose inductor, MOSFETs. Organic semiconductor capacitor or polymer capacitor are recommended for D−CAPTm mode design. The output ripple should be larger than (VOUT/0.75) x 15 (mV). In this design, two pieces of 150 μF PSCAP capacitors with 45 mΩ ESR are selected.""

     I know it is taking quite longer & bothering you. But I need to clear all the doubts.

    Thanks & Regards

    Raj Kumar

  • Hello Raj,

    There is no need for output capacitor ESR to compensate TPS51116 in current mode control. The transconductance op-amp external components give the freedom to place poles and zeros for loop compensation. It is also suitable to add a feedforward capacitor around 100pF in parallel to R1372.

    My recommendation:

    1- add 10 Ohm for loop measurement

    2- add 100pF in parallel to R1372

    Please let me know if you have further question or close the thread as resolved.