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CSD18542KTT: PCB design for the thermal resistance

Part Number: CSD18542KTT
Other Parts Discussed in Thread: CSD18542KCS, LM25116, CSD18543Q3A, CSD18534Q5A

Hello team,

Regarding following thread,

CSD18542KTT: RθJC

I discussed about thermal resistance with the customer.

The customer is considering using a PCB pattern to dissipate heat, but they are not on how to design it to withstand 100W of heat generation. I have calculated that it should be OK as long as the thermal resistance of RθJC(0.6 °C/W). How can they design it to withstand 100W of heat generation? Of course I understand that RθJC is the thermal resistance of the Junction to Top, not the thermal resistance of the Junction to Pattern.

Reagrds,

Masa

  • Hello Masa-san,

    Thanks again for promoting TI FETs at your customer. RθJC specified in the datasheet is to the tab on the bottom of the package - not to the topside. For the CSD18542KTT in D2PAK the thermal resistance, RθJC (top) is ~30°C/W. The primary path to remove the heat is thru the tab and into the PCB on which the FET is mounted. The CSD18542KCS (same FET die) in TO220 is designed to be attached to a heatsink. Can you please explain the 100W of heat generation? Is this for a single FET, multiple FETs or the system? A single FET is never going to dissipate 100W. Multiple parallel FETs attached to a heatsink would probably be required to dissipate that much power. Can you share the application and requirements?

    Best Regards,

    John Wallace

    TI FET Applications

  • Hello John-san,

    Thank you for the details.

    The customer plans to use a combination of two CSD18542KTT with LM25116.

    The customer originally planned to use a combination of two LM25116 and two CSD18543Q3A, but was informed that the system capacity would be changed from 48W (12V/4A) to 96W (12V/8A). So I examined whether the junction temperature would be an issue based on RθJC. Then I suggested CSD18542KTT because the junction temperature would exceed the recommended temperature with CSD18543Q3A.

    The customer then inquired what kind of board layout should be used to achieve the same thermal resistance as RθJC, and I posted the thread on E2E.

    Regards,

    Masa

  • Hello Masa-san,

    The link below is to an excel-based TI FET selection tool for synchronous buck converter. I made some assumptions about your application and used the tool to estimate MOSFET power losses. I don't think the CSD18542KTT is the best choice for this application. The performance will not be very good due to high power loss in the control FET. I would recommend the CSD18534Q5A in 5x6mm SON package. The original CSD18543Q3A also looks like it would work.  Iam going close this thread and will email you the spreadsheet I filled in for the application. You can try out the tool and make any changes to the requirements.

    https://www.ti.com/tool/SYNC-BUCK-FET-LOSS-CALC

    Best Regards,

    John