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TPS62087: Question about the soft-start timing

Darren (FAE)
Expert 5483 points
Part Number: TPS62087
Other Parts Discussed in Thread: TPS62097

I understand the device incorporates an internal 0.8[ms] soft-start time.
But what is the max/min?

The TPS62097 has an external SS/TR pin and gives the max/min Iss charging current.
You can use this max/min and the de-rating from the external Css cap to calculate the max/min timings...

But I don't know how to get the max/min for the TPS62087.

Regards,
Darren

  • 0
    TI__Genius 13160 points

    Hi Darren,

    I've attached the histogram of char data of soft start time over the complete temp and VIN range. There is quite a bit of statistical variation of this parameter. If you want to consider +/- 6 sigma limits like in production, this puts the max value at 6ms and min at 0ms.

    TPS62087 Sofstart char.pdf

    Best regards,

    Varun

  • 0 in reply to Varun John
    TI__Expert 5483 points

    Hi Varun,

    Egads...we're all over the place, lol...
    Hmm...

    I assume the x-axis in that histogram is our "sigma deviation" right?
    What would ~3σ be?

    Looking at the equation (tss = css * vfb / Iss) the values with the largest shift are Iss and Css.
    The xx97 device seems to be within ±0.6[ms]...(Css = 10nF±10%, Iss = 7.5uA±26.6%)

    But for xx87 to have tolerance resulting in 6[ms] for 6σ...wow, lol...
    Just because, could you double check with someone in design and see if there is another opinion floating around...?

    Regards,
    Darren

  • 0 in reply to Darren (FAE)
    TI__Genius 13160 points

    Hi Darren,

    The x axis is the soft start time in ms. You can see some tested units having a 3.2ms startup time. The characterization data reflects the real statistical behavior of the device. The integrated soft start cap has process shift, temperature and DC bias variations. The variation of course would be lower if you restrict it to the application operating temperature and VIN range. I can re-check this if you provide me with the temperature and VIN you are interested in.

    Is this already designed in or can you move to another device with a tighter spec?

    Best regards,

    Varun

  • 0 in reply to Varun John
    TI__Expert 5483 points

    Hi Varun,

    I am supporting a design with the Sitara Processor (AM65xx) that follows our reference design.
    https://www.ti.com/tool/TMDX654IDKEVM

    Attached Schematics
    See p6 and p41 for 1.8V I/O and 1.2V rails using the TPS620x7 devices.

    PROC062E4(001)_SCH.pdf

    One of the datasheet requirements is that the 1.8V I/O rail should come up before the 1.2V rail.
    But the 1.8V rail is generated from TPS62087, while the 1.2V rail is generated from TPS62097.

    They are both enabled at the same time; but it looks like there could be corner cases whereo:
     TPS62097's 1.2Vout could reach it's value before TPS62087's 1.8Vout.

    The real concern here is whether the AM65xx power-up timings are hard requirements, or there is some wiggle room.

  • 0 in reply to Darren (FAE)
    TI__Genius 13160 points

    Hi Darren,

    Is it not possible to use the PG of the 1.8V to enable the 1.2V rail? Is there any requirement on the power down sequencing. Recently we used the TPS6282x family of devices in the power tree of the latest AM62x processors (sluaak2). Since the TPS6282x family has 1A to 4A device versions it was quite suitable for AM62x. I think it may be a good option for the AM65xx as well.

    Best regards,

    Varun