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BQ76920: OCD Delay Exceeds Max Spec?

Part Number: BQ76920


We are using the BQ7692003 battery monitor chips in our smart battery design. We've built a rig that tests if chip voltage and current protections on every PCB trigger respecting the nominal protection thresholds and delays plus the tolerances listed in the battery monitor datasheet. Over-Voltage (OV), Under-Voltage (UV) and Short-Circuit-in-Discharge (SCD) protections seem to behave as expected, but trigger timings of the Over-Current-in-Discharge (OCD) protection are sometimes longer than expected and result in sporadic test failures.

We've run a series of experiments and here's what we found. For all of the following, the BQ76920 is configured as such: 8mV OCD protection threshold (with 1mOhm shunt resistor, i.e. 8A), 8ms OCD protection delay. The datasheet suggests a +/-20% tolerance on all delay options, so with the the lowest OCD delay setting of nominal 8ms we expect the OCD protection to trigger within 6.4 and 9.6ms after applying a current above the 8A threshold (+ tolerances), or between 6.5 and 9.7ms accounting for FET and FET driver delays.

But in reality OCD doesn't always trigger despite the valid conditions, even when the worst case tolerances are accounted for with extra margin:
  • Applying a discharge current >11.3A for 9.7ms results in a OCD trigger success rate between 70% and 80%
  • Applying >16A for 9.7ms results in a ~80% success rate
  • Applying >11.3A for 11ms results in a ~90% success rate
  • Applying >11.3A for 20ms results in a ~100% success rate (test couldn't be finished so this number is only implied)

Discharge current amplitude and timing was validated with a precision Hall-sensor current probe.

Please help me understand the observations listed above. Did we misinterpret the tolerance range listed in the datasheet? Are there any hidden factors we didn't account for in our analysis.

Thank you in advance and kind regards,

  • Hi Vasily,

    Past tests have shown that the OCD timer is synchronized to a 2.5 ms tick, so there is a 0-2.5ms delay before it is first detected.  So for OCD_DELAY code 0x0, the actual delay can be 7.5-10ms.  Code 0x1 is between 17.5ms and 20ms, and so on.  This could explain the time variation you are seeing outside of the OCD tolerance range listed on the datasheet.

    As for the impact that increasing the current has on OCD detection accuracy, we will need more information.  Could you please gather the voltages at the SRP and SRN pins for your test cases?



  • Hi Andria,

    Thanks a lot for your quick and informative response. We will capture the SRP/SRN voltages shortly, I'll provide an update as soon as we do.

    In the meantime, please confirm if I understood your point on the OCD trigger mechanism correctly. Here's a snippet from the BQ76920 datasheet on OCD/SCD protections (p.24):

    Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) are implemented using sampled analog comparators that run at 32 kHz, and that continuously monitor the voltage across (SRP–SRN) while the device is in NORMAL mode. Upon detection of a voltage that exceeds the programmed OCD or SCD threshold, a counter begins to count up to a programmed delay setting. If the counter reaches its target value, the SYS_STAT register is updated to indicate the fault condition, the FET state(s) are updated as shown in Table 1, and the ALERT pin is driven high to interrupt the host.

    If I get it right:

    • the sentence in bold above refers to the counter which increments at timer ticks every 2.5ms as long as analog comparators sense the SRP-SRN voltages above the programmed threshold + whatever tolerances and
    • the OCD_DELAY setting of 0x0 refers to exactly 3 timer ticks i.e. 7.5ms, setting of 0x1 to exactly 7 ticks (17.5ms) and so on
    • so the ultimate OCD trigger delay becomes
      • (0-2.5ms between comparator firing to the next tick) + (exactly 3 ticks) = 7.5-10ms.

    My questions are:

    1. Is my understanding correct?
    2. How does the +/-20% delay tolerance connect with the calculation above?

    Thanks in advance,


  • Hi Vasily,

    I believe that your understanding is correct.  The BQ76920 is an older TI part, and consequently the engineers that defined and designed this part no longer work for TI.  We have to use what we know from existing documentation and inference.

    From the documentation, I am led to believe that the +/- 20% tolerance shown on the datasheet is meant to accommodate for the tick delay, but it does not fully accomplish this. 

    For the 0x0 command, I recommend using the 7.5 - 10 ms range we discussed earlier.  This seems more consistent with the data you are seeing and what we know about the counter and tick delay.  I hope this helps!



  • Hi Andria,

    Thanks a lot for your help! Our issue has been resolved. When we took the effort to scope the voltage across the shunt resistor (SRP/SRN), we realized that the amount of time it was above the worst-case threshold for triggering OCD was shorter than we expected. As this duration was adjusted, we noticed that OCD started triggering as it should.

    Kind regards,