TPS546D24A: excessive ripple >100mV on a 1 V rail

Bahram Afghani 

First, the Square-wave Output Voltage ripple that you see on the oscilloscope is either a measurement Artifact of the grounding connections of the scope, or your output capacitors have too much parasitic inductance (ESL) in series with them, and that is forming an inductive divider with the 150nH inductor from the switching node.

The fact that the ripple voltage you are showing appears to have the switching component of just 1 of the 4-phases in a 4-phase output suggests that it is more likely a measurement artifact as an ESL issue would be far more likely to present the switching of all 4 phases rather than just one.

Your design appears to have a lot of output capacitance, likely far more than you really need, and the space required to add that capacitance could be the reason you are seeing this ripple on the output.  The design worksheet that you shared says the design needs to meet a +/- 36mV transient and 10mV cycle by cycle ripple on a 25A dynamic load change.  If that is correct, the design needs much, much less output capacitance than the 43mF currently used.

The Capacitors used in the design spreadsheet also don't match your design.  Since there is only space for 2 capacitor types, I entered the 470uF and 100uF.  Based on just those 2 capacitor sets, COMPENSATION CODE 14 should be good and the transient response is well with the design listed specification.  The additional 3,300μF, 820μF, 680μF capacitors are not helping and their placement may be adding the ESL that is introducing the 100mV step function you are observing on the output.

Here are some things to try:

1) Check the ground connections on the Scope.  The ground terminals on the scope are all shorted together, by a low impedance bus-bar inside the Scope. if two or more passive ground clips are connected to circuit at different points, the voltage difference between those points on the board will be forced across the oscilloscope probe ground leads.  If the probes are standard 10:1 passive probes, that voltage differential will then be reported as 10x higher by the oscilloscope.

For example, if the ground of the probe measuring the switching node is rising 10mV above the ground of the probe measuring VOUT when the high-side switch is turned on, the oscilloscope will report 100mV extra voltage on the Vout measurement.

2) Check the location of the Vout measurement.  If vout is measured before the output capacitors, any inductance in the power-path between the measurement point and the capacitors will appear as a step function in the output voltage, similar to that which is shown in the waveform.  With a 12V input and 150nH inductor, it takes just 1.25nH of parasitic trace inductance or ESR to produce a 100mV step waveform on the switching node. 

The output voltage ripple should be measured across the furthest ceramic capacitor from the converter, with that capacitor's ground terminal being the only oscilloscope ground measurement.  If other voltages must be measured at the same time, they should be reference to that same output ground, or measured with a ground isolating differential probe.

3) Check the layout of your capacitors.  Very large capacitor banks can add significant additional ESL, degrading the loop performance and transient response.  When possible, capacitors should be placed on both sides of the PCB and either side of the output voltage trace to minimize the parasitic inductance in series with the capacitors.  Some of the ceramic capacitors should be placed close to the inductor, with the rest placed close to the load, and the higher ESR/.ESL electrolytic capacitors placed between them.

4) Try reducing the total capacitance by removing the larger electrolytic capacitors to reduce design size and cost, while improving it's performance.

Sorry, I realize I missed one of your questions.

Bahram Afghani said:

The current consumption as mentioned above is super low right now, the regulator is at FPWM mode, is it the only mode the part supports?  do I have to change the compensation (we are at 14) to reduce the ripple within range? Reduce  Fsw?

The TPS546D24A only operates in fully-synchronous, fixed frequency mode.  It does not support phase shedding or light-load pulse frequency modulation.  If you need those features for a 4-phase 100+ Ampere output, you would need to look at a 4-phase controller with external smart-driver MOSFET power stages.  If you need light load efficiency "Autoskip" for the single phase applications, I would recommend considering the TPS549D22 in those applications.