TPSM265R1: Cadence PCB 17.x UltraLiblarian DRC errors

Daniel Waleniak

Expert 3675 points

Part Number: TPSM265R1

Dear Team,

We have an issue with understanding the documentation and generated footprint for TPSM265R1.

https://www.ti.com/lit/ds/symlink/tpsm265r1.pdf

Layout Example - Figure 10-1 - can see isolated pads with no metal

Page 29 - marked as Copper keep-out area

https://www.ti.com/product/TPSM265R1#cad-cae-symbols
Package uSIP - Download

This generates the following that gives tons of DRC errors

Please confirm that the area marked on page 29 is keep out area or disconnected copper?

Thanks,
Daniel

over 1 year ago

0 Andrew Kutzler over 1 year ago

TI__Genius 9980 points

Hi Daniel,

Per the DS, there should be no cooper in the areas between the pads.

Thanks,

Andrew

0 Daniel Waleniak over 1 year ago in reply to Andrew Kutzler

TI__Expert 3675 points

Thanks Andrew,

Will treat as keep out. Do you know why the footprint is generated with initial DRC errors though?

Best,
Daniel

0 Andrew Kutzler over 1 year ago in reply to Daniel Waleniak

TI__Genius 9980 points

Hi Daniel,

No I'm not sure why (it's probably an honest mistake). Which version of the footprint gave you those errors? I should be able to let the right people know that it's wrong, so we can fix it.

Thanks,

Andrew

0 Daniel Waleniak over 1 year ago in reply to Andrew Kutzler

TI__Expert 3675 points

Hi Andrew,

This was uSIP package for Cadence PCB 17.x.

Thanks for your help,

Daniel

0 Andrew Kutzler over 1 year ago in reply to Daniel Waleniak

TI__Genius 9980 points

Hi Daniel,

Your welcome. Happy Holidays man!

Thanks

Andrew

0 Daniel Waleniak over 1 year ago in reply to Andrew Kutzler

TI__Expert 3675 points

You as well!

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TPSM265R1: Cadence PCB 17.x UltraLiblarian DRC errors