• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 62 subscribers
  • Views 108 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28742: OVP and VDD from design spreadsheet tool

Kelvin Le THS
Expert 6475 points
Part Number: UCC28742

Hi, I have a few questions about the default example in the design spreadsheet

Q#1

In the design calculator, the overvoltage thresholds are VOUT_OVPnom = 5.3V and VOUT_OVPmin = 5.023V (calc cell C191). 

VOUT_CV = 5V, VOUTripple = 50 mVp-p (cell C163).  This means that that the maximum Vout is 5.025V (not accounting for other tolerances like the voltage regulation error).

So, the worst case Vout by design is already crossing the VOUT_OVPmin.  Should we design the minimum OVP threshold higher than the maximum Vout during normal operation?

Q#2

Is there an internal voltage clamp at the VDD pin to limit the voltage during start up charge from VBULK to VDD via RTRICK?

-Kelvin

  • 0
    TI__Mastermind 19345 points

    Hi Kelvin,

    Q1. Yes you are correct. Minimum OVP needs to be designed greater than Vout (with max ripple). You can try reducing Rvs2 resistor slightly to achieve this.

    Q2. There is no internal voltage clamp on the Vdd pin. You might need to add it externally and select zener clamp based on the Vdd voltage. The startup is governed by the following equation and is a function of (Rstr, Cdd, tstr, Istart)

    Please let us know if you have any questions.

    Thank you

    Regards,

    Harish