Other Parts Discussed in Thread: UC1843A
I am having an issue with the comp pin in the UC1843A spice model being able to be pulled down to regulate the duty ratio. It is used in the feedback loop with the FB pin to gnd so the COMP pin is high and should be able to be modulated to adjust duty ratio. It seems that in the model, the pin can not be pulled low and can source excessive currents (amps) no matter what impedance it is loaded with. In the model, it has the following comments
Model Usage Notes:
* 1. The following features have been modeled
* a. Switching frequency variation w.r.t. RT_CT pin connection
* b. Current through following pins have not been modeled
* RT_CT, COMP, OUTPUT, VC, VREF
* 2. Temperature effects, operating currrent, shutdown current are not modeled.
* 3. Current through following pins have not been modeled
* a. VCC, VFB, ISENSE
It seems from the comments, that the error amp may not simulated in this manner since the current in the comp pin is not modeled. Can someone from TI assist?