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TPS92691-Q1: Current is not regulating

Part Number: TPS92691-Q1

I've designed a switching controller using this chip for use with a large LED array. It's still in a prototype stage, so I'm using a potentiometer/voltage divider to adjust the voltage at Iadj to adjust the current.

Vin = 48 V

Vo min = 28 V

Vo max = 37.5 V

Iomax = 10.5 A

Here is the schematic.

Here is the top layer. the whole board is 90 mm x 70 mm

And the bottom layer. The only thing going on here is the ground plane for the power side, and the gate trace (nice and wide) for

I probed the pins for the IC. Here are the DC values.

Vin: 48.18 V

SS: 3.151 V

RT: 1.10 V

PWM: 7.2 V

COMP: 4.503 V

Iadj: 0.332 V (note that this depends on the position of the potentiometer)

Imon: 0.011 V

DDRV: 7.61 V

OVP: 0.577 V

IS: 0.006 V

GATE: it's kind of hard to give a DC value, as this is the switching pin

VCC: 7.6 V

I am operating this in a buck configuration.

All of those values seem about right, and the GATE pin is switching at what looks like a fairly high duty cycle.

Here is what I am observing: if I hook it up our LED array, it draws about 13 A before R8 inevitably burns, which I guess is a good thing, since that's an inexpensive and easy part to replace. This is independent of the position of the potentiometer.

If I hook it up to my eload on CR mode (constant resistance), Vout is constant, and Iout is proportional to Rload, again independent of the position of the potentiometer.

I separated analog and power grounds, connecting them through a jumper (R1). As a result, the analog signals are clean. There is virtually no noise on SS, RT, PWM, COMP, IADJ or IMON.

My question is why is Formula 31 from the datasheet not holding true. Rcs = 15 mO. If Viadj is 0.332 V, that should limit the current to 1.58 A Why is is driving 13 A? Even at when I bring Iadj down to 0, it still drives full current.

  • Hello Alexander,

    The CSP and CSN should be reversed...That's a typo on the data sheet.  In addition, you should not have a capacitor (C5) on RT pin.  

    A note is that you are trying to run almost 400W of output here and thermal is of biggest concerned.  Even with 90% efficiency there will be 40W loss on the board.  That heat has to be removed somehow.  I think you will have issue with that.  In addition, the FET and power stage components have to be designed properly. 

    Thanks Tuan

  • So CSP is pin 9 and CSN is pin 10? Methinks that needs to be changed ASAP.

  • I asked our technician to reverse those pins, and now the design works as expected.

    I definitely need to do thermal testing, but this is going to be bolted to an aluminum PCB with the LED Array, which will be bolted to a large heatsink. We're also probably not going to need to run it beyond 8.4 A, but that really depends on the optical testing which we have yet to do. It's also probably not going to run for more than 90 seconds at a time. I'll definitely lay some thermal pads between it and the aluminum PCB its bolted to though.

    I don't know who at TI is in charge of document control, but you should definitely run this up the flag pole. If I had this problem, other people will have it as well. The datasheet was release in December 2015, although there was an undocumented revision in January 2022. Either way, this needs to be rectified.

    Thank you for your help!