TPS546D24A: TPS546B24A, TPS546A24A - I2C Pullups

The TPS546D24A's CLK, DAT, and ALERT pins are designed to meet the SMBus 3.1 "High-Power" 1MHz class interface specification.

Any input voltage equal to or less than 0.8V will be read as a "Low"

Any input voltage equal to or greater than 1.35V will be read as a "High"

The pins can tolerate a maximum voltage of upto 5.5V, so they can support termination voltages from 1.62V (1.8V - 10%) upto 5.5V (5.0V + 10%)

Since the ALERT# signal is asynchronous to the CLK and DAT, there are no specific requirements for timing between the ALERT and CLK / DAT pins, so the ALERT pin can readily use a different termination voltage or pull-up resistor strength.

CLK and DAT pins however, do have some relative timing requirements, since the DAT pin is latched on the rising edge of the CLK pin.

As stated, there is no hard requirement that the CLK and DAT pins are terminated to the same pull-up voltage, since their thresholds do not depend on the termination voltage, but relative timing of their transitions is important.  Since DAT is latched on CLK rising, DAT should rise faster than CLK if there is any mismatch.

However, within those timing constraints, CLK and DAT could be terminated to different voltages, though they are generally not.