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TPS7A8300: cons of using feedforward cap

Part Number: TPS7A8300


I'm reading SBVA042.

In section 2.1 Start-Up Issue. The start-up time is divided into tref and tcff.

At t1 , the PG pin is asserted (pulled up to VOUT) when VFB reaches the reference voltage because the internal power-good comparator monitors the VFB voltage and VFB increases above the PG threshold (0.9Vref). However, it takes tCFF time for VOUT to reach the regulated voltage. tCFF is the feedforward capacitor charging time.

But I think even during tref(before PG pin asserted), the cff is already working and it needs time to be charged.

I don't understand why in figure 9b, Vout is increasing proportional to time before t1, but increased slower after t1.

  • Hello,

    You are correct. The moment that the output starts to rise, the CFF also begins to charge, so VOUT would not be equal to VREF during tref, but would instead begin deviating. The startup time of VREF is normally fast (on the order of 10's or 100's of microseconds), while VOUT can be much longer if CFF is large (as in Figure 11), so it is a close approximation that VOUT = VREF for tref when CFF is large. Furthermore, during tref when the reference voltage is still ramping, the output ramps as the superposition of an RC time constant plus the reference voltage ramp. Figure 9 is showing a somewhat more ideal example to differentiate the regions on the ramp.