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LM5113-Q1: Off impedance during transistion time

Part Number: LM5113-Q1
Other Parts Discussed in Thread: LM5113

My question is on the

Lm5113 part , the Tmon and Tmoff shows a delay matching of 1.5ns typical max 8ns I have a few questions

 

  1. What is the output impedance of the driver during that “dead” time
  2. How was the 8ns max determined?
  3. Is that a tested parameter?
  4. What is the distribution of that delay?

 

  • Hello Eugene,

    What is the output impedance of the driver during that “dead” time

    The output impedance would be the same as the driver during when it's low.

    How was the 8ns max determined?

    8ns is the worst case delay matching from -40 C to 125 C. When the chip is at room temperature or 25 C, the delay matching is typically 1.5 ns.

    Is that a tested parameter?

    Yes, the delay matching is a tested parameter. We measure the chip at different temperatures and determine the max delay matching.

    What is the distribution of that delay?

    Unfortunately, we do not have that information on hand.

    Best Regards,
    Ethan Galloway

  • 8ns is the worst case delay matching from -40 C to 125 C. When the chip is at room temperature or 25 C, the delay matching is typically 1.5 ns.,

    Is this production tested on every unit? I suspect not since you don't have a distribution.

    Also is that output impedance measured during the swing? and if so do you have data on that value as a function of time?

  • Hello Eugene,

    I've reread your question and let me try to clarify my answers. Please let me know if you have any more questions.

    The delay matching specification refers to the mismatch of the propagation delay signals. In this case, delay matching is measured as the difference between LO turning ON and HO turning OFF and vice versa. You'll notice that LO turn OFF has a propagation delay of 26.5ns and HO turn ON has a propagation delay of 28ns. The difference between the propagation delays gives a delay matching of about 1.5 ns.



    As for the impedance of the driver, it is either pulling up or pulling down. There are no other states. When powered, the driver output will always have a low impedance state.

    Also, I have found the distribution data for the delay matching. I can't share this data, but the part should perform as said in the datasheet.

    What do you mean by "Also is that output impedance measured during the swing?" ?

    Here's a link that may help you get the dead time required for the half-bridge driver: www.ti.com/.../snva815a.pdf

    Best Regards,
    Ethan Galloway

  • I guess I am more interested in the impedance on the internal devices while they switch from the i to the low totem pole, , do you keep a shoot thru current to allow for this to stay low? inside the device?

    More interested in the impedance between HOH or HOL to HS and LOH or LOL to Vss

  • Hi Eugene,

    For the impedance of HOH, HOL, LOH, and LOL, it's in the datasheet.



    The math comes out to 0.6 on HOL/LOL and 2.1 on HOH/LOH.

    Best Regards,
    Ethan Galloway