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Original question:

Using TI's encrypted MOSFET model in LTSpice- error: too few nodes

CSD18540Q5B: Why doesn't TI release a NexFET spice model ?

Jeremy Richardson
Prodigy 140 points
Part Number: CSD18540Q5B
Other Parts Discussed in Thread: TINA-TI,

Does TI not want people to use their NexFETS?  I don't understand why they won't release a generic spice model to be used on what ever spice you have you circuit  built in.  I don't see how releasing the spice model has anything to do with their IP to make this FET.

  • 0
    TI__Mastermind 36760 points

    Hello Jeremy,

    Thanks for your interest in TI FETs. There is an unencrypted PSpice model available in the CSD18540Q5B product folder. This is the standard type of model we provide for all of our FETs. Is there a particular simulation tool you're trying to use this with? Below is a link for downloading the unencrypted PSpice model. There's also the older legacy TINA-TI model which is encrypted. TI has been moving away from TINA-TI and migrating everything to PSpice. Let me know if you have any trouble with the PSpice model and if I can be of any further assistance.

    https://www.ti.com/lit/zip/slpm129

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    Prodigy 140 points

    John,

    I've been having some trouble with this model in LTspice this weekend.  I keep getting problems with it hanging or the timestep too small error.  I put 10ohms in the gate and the model will run now, but still much slower what with other mosfet models.  I'm not a spice expert.  Any ideas why the TI NexFET is causing problems?

    Regards,

    Jeremy

  • 0 in reply to Jeremy Richardson
    TI__Mastermind 36760 points

    Hi Jeremy,

    I'm not real familiar with LTSpice but assuming it is the same kind of simulator. I have had some customers experience convergence issues or long simulation times with our FET models. I believe this may be due to the tabulated capacitance subcircuits used to model the non-linear nature of the parasitic capacitances of the FET which vary with Vds (see Figure 5 in the datasheet). This approach provides a closer fit to the actual capacitances but sometimes causes these issue during simulation. Let me know if you run into any other issues.

    Best Regards,

    John