TPS40428: output ripple on board and cause system abnormal

Hello,

1- How you measure the ripple?

2- Are you using Paperclip method?

3- What is the ripple frequency? Is it the same as the switching frequency?

Regards

Hello Mahmoud,

1. I measure this ripple on the output cap vs. system GND.

2. this ripple is captured on my board with FPGA in idle state

3. I connect 40.2k to TPS40428 pin40 "RT", setting up switching freq to ~500kHz

with 2-phase operation that combined to 1MHz ripple I believe.

Regards.

Hi Alex, we want to find the root cause of the output ripple.

1- The scope picture you sent is not clear. Is the ripple frequency the same as the switching frequency?

2- can you measure the ripple at the output capacitor using Paperclip method? 

3- Using the scope probe in standard method, it picks up the switching frequency noise

Regards

Hi Mahmoud,

After a day of testing I found TPS40428 just one of the nosie source may cause abnormal on my system.

by the way here are the output waveform I captured at the capacity near the load on board reference from the cap GND

as shown there is a ~100mVripple at switching frequency

at the middle is another noise source in 70kHz

for my system spec I would like to compress the Vripple within 30mV

Regards.

Hi Alex,

1- What is the TPS40428 switching frequency?

2- Scope picture shows spikes at 163KHz

3- I don't see spikes at 70KHz

4- Is there other frequencies running on the board?

5-Can you send schematic?

Please use only one scope probe in Paperclip method and capture the ripple at output capacitor.

Regards

Hi Mahoud,

1. by calculation the switching is ~497kHz

2. I think the scope tracked the wrong peak and give 163kHz

Please refer to my cursor position giving 495kHz

3. the 70kHz is from my setup environment power, so I have not capture those noise

actually the largest peak at the middle is cause by the 70kHz noise with >100mVripple

the 500kHz noise from TPS40428 Vripple is ~100mV

4. I have another 5V and 3.3V regulator with 500kHz and 630kHz switching freq.

5. I have attached TPS40428 sch and loop calculation table in the first post

Regards.

Hi Alex,

Yes I found the schematic. Any loop measurement, in frequency domain, was done across R66? If not, we need to see the bode plots Gain/Phase and make sure the system is stable.

Regards

Hi Mahmoud,

As you said I try to capture waveform across R66 and in frequency domain, I hope it contain enough infromation for analysis

and I also put down some part no. I used in design since I worry the parts ESR may not fit for my design

100uF - TAJD107M016RNJ

560uF - 16SVF560M

47uF - GCM32EC71A476KE02K

22uF - GRM32ER71E226KE15L

390nH - FP1007R6-R39-R

Regards.

Hi Alex, 

The 560uF capacitor has an ESR of 14 mOhms, and it is in parallel to 7/47uF. The 47uF ceramic ESR is around 2 mOhms. The effective ESR is estimated around (7*47uF/560uF)*14mOhms = 8.225mOhms. 

The calculated inductor ripple current is 4.7A. So the output ripple due to ESR is 8.225mOhms * 4.7A = 38.66mV.

The output capacitance in the datasheet is purely ceramic. Please remove the 560uF electrolytic and replace it by an equivalent ceramic low ESR. We still need to check the stability using bode plots.

Regards

Hi Mahmoud,

According to loop Compensation table the change of output capacitor also require changing of the loop circuit value.

I may on hold before you can finish the bode plots review.

Thanks.

Regards.

Hi Alex,

That is right. Please let me know once you are done.

Regards

Hi Mahoud,

As I afraid of damaging my board, I using my evaluation board (no FPGA, only 2k ohm load) remove the electrolyic cap and take measure, remain 7ea 47uF ceramic cap

I see the Vpp may drop from 500mV to 200mV, but still too much for my application.

If I change my design to all 47uF ceramic cap, what will be the R/C value in loop circuit?

Regards.

Hi Alex,

Are you able to measure the loop with 7x47uF? With only ceramic capacitors the ripple should be lower than 10mV. You need to use only one scope probe in Paperclip method for correct ripple voltage measurement. The RC compensation is OK for now and the loop measurement gives more information about changing theses components.

Can you please:

1- Send scope picture for output ripple with only one probe and Paperclip method

2- measure the loop and send gain/phase bode plots

Regards

Hi Mahmoud,

I modify the output cap to 14x47uF ceramic cap and here is the output measurement in paper clip method, still see around 50mV ripple

Speaking of Vripple cause by ESR, do the cap I placed near the load also contribute to the ripple in voltage rail?

Regards.

Hi Alex,

For output ripple measurement, only one scope probe should be used in Paperclip method. Switching noise can be picked up if there is another scope probe. The ripple seems to be from switching noise.

What type of capacitor you have close to load?

Regards, Mahmoud

Hi Mahmoud,

I have used a combination of capacitor for a FPGA, including KYOCERA AVX TPM, TAJ series, KEMET T491 series and different value of 0805, 0402 MLCC

compare to the Alu cap I placed near voltage output, these caps near load have much larger ESR 

Regards.

part no.

TPME337M016R0050

TAJD107M016RNJ

T491D476K025AT

CGA4J1X7S1E106K125AC

GRM155R71H103KA88D

GRM188D71A475KE11

GRM155C71A225KE11D

GRM155R71A474KE01D

GCM155R71C224KE01

Hi Alex,

I think the caps are OK but the ripple measurement method is not correct. Do you use more than one scope probe during ripple measurement?

Regards