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TPS7A78: LDO_IN max input capacitor value?

Part Number: TPS7A78


The TPS7A78 is used for a load that takes 80mA on average, but also 280mA for peaks of about 500µs.
Since the TPS7A78 limits the output current, a 4700µF electrolytic capacitor was placed at the LDO_out. On LDO_in a capacitor of 100uF was placed. More than 100µF brought no advantage.
The circuit works fine in tests.

However, the data sheet says that the capacitor at LDO_in = 10 x LDO_out and the values in the "recommended operating conditions" should be max. 1000µF and 100µF respectively.
What speaks against the solution that was tested?
What is the background behind the LDO_IN recommended operating condition above?
Are there some potential risks with this approach that would for example reduce the TPS7A78 life time?

The project is close to production and the preference would be not to do any change in the HW.
The start-up time is of course long, but this is not a problem in this application as long as we wait for Power Good

Thanks in advance,


  • Hi Anber,

    The primary issue is to prevent the LDO_IN from drooping during a transient event, such that the UVLO is tripped.  By placing those large capacitors you are effectively holding up the voltages during your brief high current transient event for 500us.  The charge pump off of SCIN and to the LDO_IN can only deliver a limited amount of charge to replenish LDO_IN during a load step on LDO_OUT.  As long as you don't experience heavy voltage drops on LDO_IN as the LDO tries to recover, you will be fine.

    Do you have a ceramic capacitor in parallel with your 4.7mF electrolytic capacitor?  What is the maximum ESR you expect from the electrolytic capacitor?  I'm worried about a possible instability from this capacitor.  Once you give me the ESR I'll look into it and get back to you.



  • Hi Anber,

    I assume you are already aware of the current limit of this device which is copied below from the datasheet.  Current limit of LDOs usually have a bandwidth of around 50us, so a 500us transient will likely enter current limit which means you will see droop out of the 4.7mF capacitor at this time of about 8.5mV.  But, you have tested this and I assume have already seen this droop, but I wanted to let you know about the current limit just in case.



  • Hi Stephen,

    yes, the idea behind the 4.7mF electrolytic is to circumvent the current limit. We have a 100nF ceramic in parallel on LDO_OUT. We have not yet selected an electrolytic, what would be the requirement on the ESR?

    Thanks for the quick support!


  • Hi Wolf,

    The ESR of the output capacitor will want to be less than 200 m-ohms.  Take a look at your electrolytic capacitor across your operating temperature and tolerances to assess whether it meets this condition.  If not, then add a ceramic capacitor in parallel with the electrolytic, 1uF is enough but 10uF is also fine, etc.  This way your effective impedance across frequency will meet the 200 m-ohm condition due to the parallel combination of the electrolytic and ceramic capacitors.  The 100nF is not enough unfortunately as it will not resonant until greater than 10 MHz and we need it to resonate at lower frequencies.