LM3409: With PFET of Qg greater than 30nC

Taito Takemura

Part Number: LM3409

Hi team,

My customer is designing PFET with 36nC and LM3409 and has some questions about them.

9.1.8 of the LM3409 datasheet states that if Qg is greater than 30nC and CF is between VIN and VCC, the current detection will be erroneous. I can't understand the mechanism of error detection by reading at the datasheet. Could you please tell me more about the mechanism of this current detection misidentification? Also, could you please explain why a small DC offset causes when Cf is placed between the Vcc and CSN pins?

Thank you for your help.

Regards,

Taito Takemura

over 1 year ago

0 Xiaoguang1 over 1 year ago

TI__Genius 14120 points

Hi, Taito-San,

will reply you soon

+1 Xiaoguang1 over 1 year ago

TI__Genius 14120 points

Hi, Taito-san,

I draw draft as below and hope it can help understand it easier. With CF connected Vin, Igate current which is offered by Cf is also sensed together with ILED current when Q1 gate is charging . With large Qg, Igate becomes more significant.

With CF connected to CSN, Igate will flow from CF to CSN instead of CSP, bypassing RSNS resistor. See below.

However, there is still average current flowing through RSNS to charge CF to VIN after CF discharges. This causes a small DC offset in VCST.

0 Taito Takemura over 1 year ago in reply to Xiaoguang1

TI__Intellectual 1640 points

Hi Xiao,

Thank you for your answer. It is very helpful.

Thanks,

Taito Takemura

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LM3409: With PFET of Qg greater than 30nC