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UCC28781-Q1: Depletion mosfet at >1kV

Part Number: UCC28781-Q1
Other Parts Discussed in Thread: UCC28C56EVM-066, UCC28781

It seems that >1kV depletion nmos costs a fortune, therefore i am looking for other possible solutions.

Maybe a zener to drop 30V via high voltage resistors? Problem is i dont know how much current SWS really needs to keep the system stable. Please let me know.

Thanks in advance

  • Hello Valentinas, 

    The SWS input performs two functions: Start-up and ZVS sensing.  
    Your zener circuit proposed above would solve/allow only the start-up function.  (The depletion-FET normally allows 1-2mA of dc start-up current. In this mode, stability is not an issue.)

    The proposed circuit disconnects the sensing FET from the switched node, so after start-up, there will be no detection and control of the ZVS point of the waveform.  Without this sensed feedback to the ZVS tuner block, the tuner would saturate to one side and keep PWMH on for the maximum time the tuner allows.  PWMH signal drives the SR_FET which allows reverse current to set-up negative current in the transformer to achieve ZVS.  With excess negative current, efficiency would be very low and it may not be possible to pull full power from the converter.   

    TI has recognized this issue and developed a suitable method that accommodates high voltage inputs.  Currently there is a patent application pending and I have requested an update of its status.  I will relay this status to you as soon as I receive a reply.  Unfortunately, until the patent is granted I cannot provide anyone any information about it.   

    Regards,
    Ulrich

  • What if we dont disconnect from the Q2 drain and instead connect the voltage divider network to that node? Then the IC should be able to sense the switching node? Or would there not be enough current for that?

  • Hi Valentinas, 

    The SWS input needs to sense the Q1 drain voltage without attenuation and the depletion-FET provides that signal while clamping it to about 15V to protect SWS from the high voltage.  

    I've been informed that the patent paperwork is complete and I am able to show the cascode arrangement for SWS from higher voltages.

     Here, HVG is the same as P13 pin of the UCC28781-Q1.

    Essentially is comprises two lower-voltage depletion Fets (like BSS126) connected in series, with supporting components. 
    Two 600-V Fets extend this function to 1200V peak switched node voltage. A 600-V plus 800-V Fet extends it to 1400Vpk, etc. 
    Additional Fets can be cascoded to raise the voltage even higher: 

    Vz are zener diodes stacked to a clamp voltage such as 450V (3 x 150V each) to protect the down-stream D-Fet with margin to its rating. 
    Rz is 1Meg, and Cff is 1pF.   Cff is used to distribute the switched node dv/dt to the zeners faster. 

    Please consider this arrangement for your UCC28781-Q1 system.

    Regards,
    Ulrich

  • Thank you very much Ulrich, i am excited to try this approach.

    In EVM there is this D6 and R24, are they not needed anymore? 

  • Hello Valentinas, 

    I recommend to keep them in place on the lowest Fet in the stack.  
    I think the internal document from which I copied the figures did not show them to avoid cluttering up the diagram and distracting from the circuit. 

    R24 is needed to provide a discharge path for stray charge when no power is applied to the system. 
    D6 is a protection device that normally does not do anything, but is there to protect the Vgs "just in case" some severe transient event upsets the bulk rail or switched-node.      
    Actually, I don't know if a TVS is needed on each FET or just the bottom one.  I'll see if I can find out, but I'm not sure when I'll have an answer. 

    Meanwhile, a form of this structure has already been used on the UCC28C56EVM-066 board: https://www.ti.com/lit/pdf/sluucn1 
    There, it is used for start-up only and has an extra control on the lower gate that the UCC28781 circuit does not need. 

    Regards,
    Ulrich