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TPS546A24A: Switching noise cause failed PMbus

Part Number: TPS546A24A
Other Parts Discussed in Thread: TPS546D24A

Hi TI team,

I'm using TPS546A24A in my design.

But when I measured PMbus i saw the periodic noise and I found that noise is synchronized with switching waveform. Please see the picture below ( the top is SCL signal and the bottom is measured at the output inductor)

Another image noise on SCL and SDA

I see that the noise is bigger when SDA and SCL is low state.

Please see our layout in below picture

Do you have any method to overcome this noise?

Thanks,

  •  

    Are you seeing failed PMBus transactions?  The waveform you posted appears to show a valid and completed PMBus read transaction.

    What you appear to be seeing is ground differential noise and scope pick-up from the PMBus when the TPS546A24A is pulling the CLK or DAT pins to its local ground, which is also why you see a lower "low" voltage on the CLK and DAT pins at specific times during the operation - the TPS546A24A's CLK and DAT pull-downs are much stronger than the bus controller's pull downs.

    SMBus and PMBus define the CLK and DAT pins as requiring a minimum 50ns glitch filtering on both CLK and DAT specifically to prevent ground differential noise, like this switching noise, from affecting the measurements.  In addition, when pulled low, the noise would need to exceed 800mV or fall below 1.35V when the bus is high before the noise would be able to corrupt the data transmission.

    I do not see any sign of any of the noise you are showing coming close to the value that could corrupt the transaction.

  • Thank Peter,

    You're correct. Currently, coupling switching noise does not cause the failed transaction

    But It's failed Absolute Maximum Ratings on SDA and SCL. As you see on the waveform, the lowest voltage is around -450mV

    Has any potential damage happened?

    And I have another question. If the noise appears at the edge, the non-monotonic issue will happen. Could the 50ns glitch filtering handle the non-monotonic issue?

  •  

    But It's failed Absolute Maximum Ratings on SDA and SCL. As you see on the waveform, the lowest voltage is around -450mV

    Has any potential damage happened?

    The waveforms you are seeing are the CLK and DAT pins tracking the TPS546D24A's AGND voltage as it deviates from the ground sense of the Oscilloscope.  Since the Absolute Maximum ratings are with respect to the TPS546D24A's AGND pin voltage, there is no risk.

    The ground noise is seen when the CLK / DAT pull-down inside the TPS546D24A's internal pull-down is "ON"  The internal pull-down has a maximum resistance of less than 20Ω to meet the 0.4V @ 20mA specification for 1MHz class SMBus.

    And I have another question. If the noise appears at the edge, the non-monotonic issue will happen. Could the 50ns glitch filtering handle the non-monotonic issue?

    Yes, the 50ns glitch filter will handle any non-monotonic rise/fall of the CLK or DAT pins.  The internal net monitoring the external pin voltage requires the external pin to cross the transition threshold and remain crossed for 50-80ns before the internal net changes.  If the external pin returns to its prior state for more than 5ns, this 50-80ns delay will reset. 

    Starting from a high idle state, a stream of 50ns lows with 5ns highs between them will be ignored by the pin.

    Starting from a low state, a stream of 50ns highs with 5ns lows between them will also be ignored by the pin.

    This is intended to allow the TPS546D24A to ignore I3C traffic on its bus.