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TPS7A8300: TPS7A8300 output bumped up

Part Number: TPS7A8300

Hi TI experts,

I used TPS7a8300 in my design to generate A1.8V from A2.5V. There is another power rail P3V3_Z0 which was enabled ~550ms later than A1.8V. 

Observed once P3V3_Z0 is enabled (ramped up), A1.8V is bumped up from 1.8V to 2.1V.

I manually added a 100ohm bleeding resistor on A1.8V, then no bump up any more.

Why TPS78a8300 can be charged up to 2.1V and stays stable at 2.1V? Measured FB voltage, it got bumped too. Looks the control loop can't turn FB voltage back to Vref.

Why a 100ohm bleeding helps here? Given 100ohm will have only 18mA loading current on A1.8V.

Yellow-- P3V3_Z0

Red-- A1.8V

Thanks

Neo

  • Hi Neo, 

    Thank you for reaching out and sharing this with us. 

    Is the P3V3_Z0 near the TPS7A83 and/or does it share any rails with the LDO? 

    Is R1145 connected? Can you also share the layout for the PCB? 

    What is the load for the LDO? 

    Also, although the ratio of the FB network is ok, Table 3 from the DS shows the following: 

    Have you tried using recommended R values? 

    Best, 

    Edgar Acosta

  • Hi Edgar,

    I don't see directly interfere between power shape, the two power regulators are placed far from each other.

    But looking at the waveforms, P3V3_Z0 is pre-biased once A1.8V ramps up. so i suppose there is some leakage current between these two rails.

    However, even there is leakage (from P3V3_Z0 to A1.8V after P3V3_Z0 is ramped up), why TPS7a8300 can not turn voltage back to 1.8V?

    R1145 is there but right side of R1145 is left floating. so no voltage margining from external.

    LDO load is designed for 0.1A max, but should be very small loading at beginning of board power on.

    For FB divider, actually there are 4x same LDO/divider designs for this board, rest 3x are working fine, only saw voltage bump up on this 1.8V rail.

    Thanks

    Neo

  • ...

    Yellow -- P3V3_Z0

    Red -- A1.8V

  • Hi Neo, 

    Thank you for sharing a snippet of the Layout. 

    I do see some overlap from the Yellow -- P3V3_Z0 to the Red -- A1.8V. Is there any GND planes separating these planes? Is there anything that the Yellow is powering near the A1.8V? 

    This might be hard to do, but is there a way to configure the LDO using the ANY-OUT pins instead of using external resistors? 

    Also, can the 3.3V rail be turned on first without bringing the TPS7A83 on and check for any leakage and/or voltages when the TPS7A83 is off? Furthermore, can the TPS7A83 be turned on after to see if this behavior still holds? I assume yes but want to verify. 

    If there is leakage to the FB pin, then this will remain until the device sees a power cycle and/or as you already mentioned, use an R to bleed some of this current. 

    Were the FB resistors changed to the recommended values? Can you also remove R1145. Although you mention that it is floating and there is no margining, we want to discard any other possible leakage path. 

    Best, 

    Edgar Acosta