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TPS40210 design loop compensation

Anshul Satija
Prodigy 40 points
Other Parts Discussed in Thread: TPS40210, LM3488

Hi All,

I have been trying to make this boost converter design using TPS40210 which has the following specs:

Input- 11 to 14 volts

Output - 16 to 21 volts

Output current - 4 A

I am not familiar with loop compensation in power supplies and so,I have decided to take the help of Switcher Pro design tool.

I need help in finalizing the compensation components as when I increase the inductance's value to 33uH to reduce ripple current, the design shows insufficient gain margin(6 dB) warning.

The values which I have used for the compensation loop are:

(10nF,18.7k) and 270pF.

I read somewhere that low gain margin doesn't mean instability but the response time will be longer.

Should I go ahead with these values or can anybody please help me in finding the best possible values for my entire specification range?

I have been breaking my head over this for the past few days now but I am not able to find a solution.Any help would be highly appreciated.

Regards,

Anshul

  • 0
    TI__Genius 17240 points

    Hi Anshul,

    I think the compensator design is good. You can go ahead with these values. 

    I have put the parameters you have into SwitcherPro, the frequency where the gain margin is given is way above switching frequency. Since the model is not accurate after 1/2 of switching frequency anymore, the prediction of gain margin is not accurate.  

    If you want to design the compensation by youself, you can follow the procedure given in the datasheet. The design example 1 gives step-by-step design procedure.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 40 points

    Hi Na, 

    Thanks for the quick reply.

    Actually, I had used the procedure mentioned in the datasheet for error amplifier compensation design.

    My load comprises of all kinds of commercially available net-books in the market whose output voltage range varies from 16 to 21 volts and the output current can go up to a maximum of 4 A.

    While calculating the value of compensation loop components from the procedure, I have assumed minimum load to be 0.5A and the output capacitor's ESR to be 10 milliohms(max).

    I have put two 4.7 uF capacitors in parallel with the electrolytic to increase current handling capacity.

    When I put the desired loop crossover frequency to be 20 kHz, inductor's value as 33uH and the sense resistor as 10 milliohms,I get the following values :

    (5.14nF,15.48k) and (102.8 pF)

    I have attached the schematic which I have used.

    I am changing the output voltage through an arrangement of potentiometers and resistors.

    Could you please tell what kind of impact does changing the output voltage have on the compensation network and the current limit part?

    And will the circuit be able to handle inrush currents that occur on start-up.My input voltage source is a battery whose voltage can vary from 11 to 14 Amperes.

     

    Regards,

    Anshul7610.dur0003_SCH.pdf

  • 0 in reply to Anshul Satija
    TI__Genius 17240 points

    Hi Anshul,

    According to equation (9) on page 15 of the datasheet, the downslope of the current sense waveform increases when VOUT increases. In order to avoid sub-harmonic instability, the current sense resistor should be designed for maximum VOUT as given in equation (10), so  that the internal compensation ramp signal  is greater than half of the down slope of the current ramp signal at the worst case.

    According to equation (58) on page 30 of the datasheet, current mode controlled boost converters have higher gain with higher output impedance. Therefore, the compensation should also be designed at maximum VOUT.

    Regards,

    Na

     

  • 0 in reply to Na Kong
    Prodigy 40 points

    Hi Na,

    So that means the maximum output voltage that I have chosen(21 V) for the compensation and current sense resistor selection is correct,right?

    But the thing is I was getting different values of the compensation components when I used the equations given in the datasheet(I mentioned the values in the above post also) from the values that I am currently using( 10nF,18.7k,220 pF and 10 milli-ohms for the sense resistor).

    But you said that these values would also make a good compensator design.So,for now, I have decided to stick with these values and will test the boards out when they arrive.

    Btw,I had another minor doubt.Actually, I read from an article somewhere that putting electrolytic and ceramic capacitors in parallel puts a lot of stress on the electrolytic capacitors as sometimes,almost 70% of the ripple current can flow through them causing excessive heating.I wanted to know the reason behind this because as per my knowledge,the ESR of ceramics at high frequencies is very low as compared to that of the electrolytics and by this logic,most of the current should be handled by the ceramics alone.

    I have used a 150uF/35V(with a ripple current rating of 850mA) electrolytic capacitor at the output along with two 4.7uF/50V capacitors.The output ripple current that this capacitor combination should be able to handle for my application is 3.92A,my question is whether this combination of capacitors that I have used will be able to handle this high an output current without excessive heating in the electrolytic output capacitor.

     

    Regards,

    Anshul

  • 0 in reply to Anshul Satija
    TI__Genius 17240 points

    Hi Anshul,

    So that means the maximum output voltage that I have chosen(21 V) for the compensation and current sense resistor selection is correct,right?

    Yes.



    But the thing is I was getting different values of the compensation components when I used the equations given in the datasheet(I mentioned the values in the above post also) from the values that I am currently using( 10nF,18.7k,220 pF and 10 milli-ohms for the sense resistor).

    But you said that these values would also make a good compensator design.So,for now, I have decided to stick with these values and will test the boards out when they arrive.

    The two sets don't have huge difference for compensation. The dominant pole frequency is the same. You can go with either one.


    Btw,I had another minor doubt.Actually, I read from an article somewhere that putting electrolytic and ceramic capacitors in parallel puts a lot of stress on the electrolytic capacitors as sometimes,almost 70% of the ripple current can flow through them causing excessive heating.I wanted to know the reason behind this because as per my knowledge,the ESR of ceramics at high frequencies is very low as compared to that of the electrolytics and by this logic,most of the current should be handled by the ceramics alone.

    I have used a 150uF/35V(with a ripple current rating of 850mA) electrolytic capacitor at the output along with two 4.7uF/50V capacitors.The output ripple current that this capacitor combination should be able to handle for my application is 3.92A,my question is whether this combination of capacitors that I have used will be able to handle this high an output current without excessive heating in the electrolytic output capacitor.

    I am not sure where is the 70% coming from. Here is my understanding. I agree with you that the major portion of the ripple current will go through the ceramic cap. But output voltage ripple on the ceramic cap is the same voltage applied to the electrolytic caps, which will induce current flowing through the electrolytic cap. Assume the output voltage ripple is Vout,ripple and the ESR of the electrolytic cap is ESRelect. Then the RMS current flow through the electrolytic cap is

    Irms,elect = Vout,ripple/(sqrt(12)*ESRelect)

    You can calculate this value based on your design. 850 mA maybe low.

    Regards,

    Na

  • 0 in reply to Na Kong
    Prodigy 40 points

    Hi Na,

    I am giving you the link of the article where I saw the 70% ripple current part. Actually, the article is for selecting the input capacitor for a buck converter but he has written about the electrolytic and ceramic capacitor combination only.

    http://www.eetimes.com/design/power-management-design/4012532/Power-Tip-21-Watch-That-Capacitor-RMS-Ripple-Current-Rating-

    Another problem is that I have not been able to find the ESR rating of a 4.7 uF/50V ceramic capacitor anywhere in the datasheets due to which I can't calculate the exact value of output voltage ripple.Most manufacturers only give the value of the capacitance and its rated voltage. 

    If I estimate the output ripple voltage to be 500 mV which is what I am expecting, then the ripple current in my electrolytic capacitor comes out to be 1.8A according to your formula(ESR of the electrolytic capacitor is 80 milliohms) which is way above the rated current of 850mA.

    When the inductor is getting charged , then the output capacitor combination should be able to supply the whole load current, right?How is current divided among the ceramic and electrolytic capacitors during this interval?They haven't mentioned anywhere in TPS40210's datasheet about the ripple current in the output capacitor but I found one formula in LM3488's datasheet which states the formula for the maximum current through the capacitor  in a boost converter during the interval when the inductor is getting charged.

    I want to ask if my selected combination (150uF electrolytic + two 4.7uF ceramic) is going to work or not for a maximum of 4A load current?I think the way I have written my query is quite confusing. Please clarify if you don't understand my doubt.

     

    Thanks and Regards,

    Anshul

     

  • 0 in reply to Anshul Satija
    TI__Genius 17240 points

    Hi Anshul,

    For a better estimate of the ripple current in output capacitors during steady state, you can also run a simulation.

    During the start-up time, the equation (14) of TPS40210's datasheet gives the formula for the charging current to the output capacitor. It is much smaller than the steady-state ripple current. I think even when the inductor is getting charged, it is still the input supply providing the load current through the inductor, not the output capacitors. From another perspective, if the load current is purely provided by the output capacitors, the output voltage will drop and the feedback control will get into the picture and try to pump in more energy by increasing the duty-cycle. Hope this explanation helps.

    Regards,

    Na