BQ76952: AFE Overheating during adjacent cell balancing

Embedded Developer

Part Number: BQ76952
Other Parts Discussed in Thread: TIDA-010247

Hello,

We are using stacked bq76952 configuration as per TIDA-010247 reference design. Up until now we've been balancing alternate cells, recently we decided to use the adjacent cell balancing feature.

When 2-3 adjacent cells are being balanced it works fine, but when the number of balancing cells increases further the AFE starts to overheat and reach around 90-100 degree Celsius (Observed via thermal camera), and the internal temperature cutoff of the AFE turns off the balancing.

We are using Rbal = 22 Ohm, Rn and Rn-1 = 100 Ohms, Rgn = 10 kOhm and Cn as 220 nF

The Gate Threshold voltage of the external NFET is ~0.8V

And the input cell voltage was around ~ 4V

What would be your recommended solution for this

Thank you

over 1 year ago

0 Luis H. S. over 1 year ago

TI__Mastermind 27470 points

Hello Embedded Developer,

We usually do not recommend adjacent cell balancing (albeit it is allowed). It is likely that having them balancing adjacently is causing a larger current to flow through the internal cell balancing resistors causing a larger power dissipation and over-heating the AFE. I would limit the amount of adjacent cell balancing to 2-3 if this works.

We have not tested adjacent cell balancing directly. The best recommendation for this solution would be to limit the amount of adjacent cells being balanced at a time. You could also adjust the duty-cycle of the cell balancing.

May I ask, why do you want to cell balance so many cells adjacently?

Best Regards,

Luis Hernandez Salomon

0 Embedded Developer over 1 year ago in reply to Luis H. S.

Prodigy 180 points

Hi Luis,

What is the difference in balancing 8 alternate cells vs balancing 8 adjacent cells? Is there a difference in power dissipation?

We are exploring adjacent cell balancing in comparison with the alternate balancing to finalize the balancing algorithm.

Thanks for prompt response

Regards

+1 Luis H. S. over 1 year ago in reply to Embedded Developer

TI__Mastermind 27470 points

Hello ED,

The way it works should be the same. There will be some voltage drop on the Rdson of the internal FETs due to the cell balancing. All this can add up to increase the overall power dissipation, especially since there will be a larger voltage across the internal balancing resistors. There will also be some other cell balancing current flowing through the middle adjacent cells, since these are still connected through their respective 100-Ohm to the internal balancing resistance.

We have not tested adjacent cell balancing with this device's family, so I am not sure if we understand all of the cases that could occur when balancing many cells adjacently. But the biggest concerns should be the power dissipation and VC0 ABS max being exceeded. How these are affected may be something you will have to characterize. If you can estimate the currents going into the pins during adjacent cell balancing, it may give an idea of how much power is being dissipated. It is difficult to visualize how all the currents would flow normally.

Another thing is that if using external cell balancing, some of the FETs may not be able to turn-on effectively due to the way the current is flowing with adjacent cells, which would be different the more you add together.

I would limit the adjacent usage to 2-3.