LP8733: Enable and disable control with the EN pin

Hi Daisuke,

Can you share a schematic of the LP87334D? Also can you confirm the time that EN is low? it appears to be ~200ms, is this correct?

Thanks,

Daniel W

Hi Daniel-san,

Thank you for your reply.

Can I use a private message to share our customer's schematics with you?
How can I send a private message to you?

The time when EN is low is about 200 ms.

Best regards,

Daisuke

Hi Daisuke,

I have sent a friend request. Please accept it and then you should be able to direct message the schematic.

Thanks,

Daniel W

Hi Daniel-san,

Thank you for your reply.

I have sent a private message to share our customer's schematic with you and I would appreciate it if you could review it.

Best regards,

Daisuke

HI Daisuke,

Thank you for sharing the schematic. I will review and provide feedback in the next 2 days.

Thanks,

Daniel W

Hi Daisuke-san,

I do not see any immediate issue with the schematic that would be causing this issue. Can you provide a scope shot of BUCK0, BUCK1, LDO0, and LDO1 shutting down?

Thanks,

Daniel W

Hi Daniel-san,

Thank you for your reply.

Attached are the scope shots of the shutdown with each of power outputs.

Incidentally, even if the EN pin was held Low for more than 10 seconds, it did not power on as well.

We suspect that shutdown by the EN pin is not a reset factor and therefore cannot be powered on.

In the section "7.3.7 Device Reset Scenarios" on the datasheet, the following two reset methods are described, which do not include shutdown by the EN pin.

• Software reset with the SW_RESET bit in the RESET register.
• Undervoltage lockout (UVLO) reset from the VANA supply.

Best regards,

Daisuke

Hi Daisuke,

The reset by RESET register and VANA UVLO refers to a reset of the device digital core, not the outputs.

Can you check the nINT level during power down?

Also are you able to access the device via I2C?

Thanks,

Daniel W

Hi Daniel-san,

Thank you for your reply. Sorry for the late reply.

After shutdown by the EN pin, nINT is also asserted low.

Checking via I2C, OVP_INT in INT_TOP_1 register is set. And VSYS (VCC_5V) seems to be overvoltage at the start of power-down.

After reset by SW_RESET or clearing OVP_INT, power-on by the EN pin succeeds.

When VSYS (VCC_5V) is set to about 4.5V as a trial, OVP_INT is not set and then power-on by the EN pin succeeds.

Best regards,

Daisuke

Hi Daniel-san,

Thank you for your reply. Sorry for the late reply.

Our customer would place larger capacitors on the 5V line. They may also use the FPWM version of the back converter for the 5V supply in their next design.

Best regards,

Daisuke