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UCC14240-Q1: datasheet question

Part Number: UCC14240-Q1
Other Parts Discussed in Thread: UCC14240EVM-052

① What is the status of ““Mama” burst” and ““baby” burst” on page 19 of the data sheet?
② If the output is single as shown in the figure (8-2) on page 27 of the data sheet, where does COM correspond in the circuit diagram?
③ What is the value of Percent_Cdroop in formula (1) on page 28 of the data sheet?

④Regarding the following descriptions on the 1st to 3rd lines of the data sheet P17
"The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a heavy load to (VDD – VEE) or (COM – VEE) outputs until the /PG pin has indicated power is good (pulling logic low) to avoid problems providing the power to ramp-up the voltage.”

It states that heavy load should not be applied between VDD and VEE until the PG pin goes low, but how much load can be applied? I would like to have the numbers if you have them.
In our current design, the secondary output end of UCC14240 is connected to the input end of the drive IC and other ICs, and a max27mA load (without PWM) is pulled before PG goes low. I would like to confirm whether there is a problem with the specifications.

• Hi,

① What is the status of ““Mama” burst” and ““baby” burst” on page 19 of the data sheet?

[Hong] UCC14240EVM-052, you can see both mama burst and baby burst behavior and status.

② If the output is single as shown in the figure (8-2) on page 27 of the data sheet, where does COM correspond in the circuit diagram?

[Hong] COM = VEE

③ What is the value of Percent_Cdroop in formula (1) on page 28 of the data sheet

[Hong]

• Cout2 calculation shown in (1) mentions "Percent_Cdroop", what is it?

During the time when the MOSFET gate drive change from low to high, the current from the capacitors will discharge the capacitors, so the capacitors voltage will change to a bit lower than before the drive turn on. Say, 18V is before the turn on, and you allow 5% drop, it means, during the gate turn on, the capacitor voltage can be as low as 17.1V, so the 5% is the droop in percentage, so Percent_Cdroop = 5

④Regarding the following descriptions on the 1st to 3rd lines of the data sheet P17
"The output load must be kept low until start-up is complete and PG pin is low. When powering up, do not apply a heavy load to (VDD – VEE) or (COM – VEE) outputs until the /PG pin has indicated power is good (pulling logic low) to avoid problems providing the power to ramp-up the voltage.”

It states that heavy load should not be applied between VDD and VEE until the PG pin goes low, but how much load can be applied? I would like to have the numbers if you have them.

In our current design, the secondary output end of UCC14240 is connected to the input end of the drive IC and other ICs, and a max27mA load (without PWM) is pulled before PG goes low. I would like to confirm whether there is a problem with the specifications.

[Hong] It is basically about 10% of your full load. So you need find how much percentage from 27mA over your full load current. If you use this device only to bias the gate driver, then you do not need worry about, but if you also want to use it bias something else, then you need to be careful arranged - it is basically to note that if you have too much load and the device cannot completer soft start within 16ms, then the device cannot start up.