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LM25148: Vout drop above 3 Amps

Part Number: LM25148
Other Parts Discussed in Thread: LM25149-Q1


I've designed a board with LM25148 to reach 5V out @ 8A with 15V in.

I've used the datasheet and WebEnch to create the design.

I'm testing the design with an electronic load. It's ok upto 3.0A with VOut = 5.02V .

At 3.1A, PGood goes low and VOut fall to 4.33V. VOut stays at 4.33V upto 5A. I can reach 11A with VOut=3V.



Top Layout

Top Layout

No Load

No Load: C2->LO ; C3-> SW; C4-> HO;  Math -> HO Minus SW


2A Load. VOut = 5.02V


4A Load, VOut drops to 4.33V

Any idea or clue ?

Thank you for your help.

  • Hi Jean,

    Are you measuring these gate drive HO and LO signals at the IC or at the FET?

    What does the SW node look like when VOUT drops at 4A? Is it stable? Also is your VIN stable at that condition?

    Can you attach a quickstart calculator? 

    I think your HO and LO traces should be thicker, you need 20mil traces.

    Also the LM25148 location should be placed to minimize the length of the gate drive traces. Right now it looks like you have a very long LO trace.

    Is this a two layer design? You should add a current sense filter to filter noise from ISNS+ and VOUT signals.

    See LM25149-Q1 EVM schematic and layout for reference. 

    Let me know,


  • Hi Orlando,

    The signals are measured  at the FET. SW seems stable to me, but, what is "stable" ?

    0118.LM5148-LM25148 Quickstart Calculator_rev3.xlsm

    I attached the calculator.

    You are right, my FET traces are only 11mils and LO (36mm long) is much longer than HO (26mm long) .

    The design is 4 layers. Shall LO and HO signals be on different layers ?

    I've tried the ISNS+ filter but it doesn't change the behavior.

    I've added the boot diode and this helps. I can now go to 4.2A. Why ?

    I've then double the SW, LO and HO trace with flying leads and I reach impressively 7A.

    I will redesign the board and let you know.

    Thank you,


  • Hi Jean,

    Yeah, your LO signal looks like some self-turn on is happening. This is when SW and HO are capacitively coupling to LO, via the low-side FET's  parasitic gate-to-drain capacitance.

    You can see the LO rings just as SW node rises, and if this rings above the FET threshold, then the low-side FET might self turn on at the same time as the high-side FET.

    Thicker traces (or flying leads) decreases trace resistance and inductance, and the pull-down of the low-side driver can keep the low-side FET OFF much better.

    Not sure why boot diode helps, maybe it helps increase boot voltage and HO drive strength. 

    Also HO and SW should be differentially routed to high-side FET.

    Ideally LO and HO should be on different layers, however with 4 layer it's probably difficult as the second layer should be a GND layer, but yeah it should be OK to have HO and LO traces on the same 3rd layer, just keep GND copper between these two traces.

    Hope this helps,


  • Hello,

    I finally received my new prototype board.

    Better placement, shorter and thicker traces solved the problems.

    Thank you.