Other Parts Discussed in Thread: PSPICE-FOR-TI
Hello,
I am using TPS7H5001 and need to simulate it in LTspice. I ran the .lib file from the Design Resources, taken from the PSpice Buck converter design. I have errors when running this model. Notice that with an input of 10V, the soft start voltage reaches 1.5V but the the other traces do not have data or are not plotted.
1. Can you help me determine if my circuit is correct for testing the general Datasheet behavior. I am specifically validating for SP and PS times relative to OUTA and OUTB at approx 200kHz and how they vary with there respective resistances (SP and PS) ?
2. How do you buffer connect an OTA? Is the shorting COMP to VSENSE correct?
3. Can you help me determine why I am seeing SRA, SRB, OUTB and OUTA collapsed? OUTA comes up but there does not seem to be anymore data that plots. Is it a schematic error or is it that the model does not work on LTspice ?
4. Is the model good for LTspice use or it exclusive to PSpice? ( I ran this on PSpice and the simulation crashed or did not give meaningful information)
Attachements:
1. .lib model used.
2. LTspice image of Circuit and Sim results.
3. LTspice error image
4. LTspice simulation file. --> change the .txt extension to .asc please.
TPS7H5001_5 - LTspice_simy.txt
Version 4
SHEET 1 1080 20620
WIRE 592 -272 -608 -272
WIRE -80 -144 -464 -144
WIRE -48 -144 -80 -144
WIRE 32 -144 -48 -144
WIRE 352 -144 272 -144
WIRE -464 -96 -464 -144
WIRE -48 -96 -48 -144
WIRE 32 -96 -48 -96
WIRE 352 -96 272 -96
WIRE -608 -64 -608 -272
WIRE -80 -48 -304 -48
WIRE 32 -48 -80 -48
WIRE 352 -48 272 -48
WIRE -304 -16 -304 -48
WIRE 32 0 -224 0
WIRE 976 0 272 0
WIRE -464 16 -464 -16
WIRE -224 48 -224 0
WIRE 32 48 -224 48
WIRE 832 48 272 48
WIRE 976 48 976 0
WIRE -224 96 -224 48
WIRE 32 96 -224 96
WIRE 448 96 272 96
WIRE 720 96 448 96
WIRE -304 128 -304 48
WIRE -224 128 -224 96
WIRE 832 128 832 48
WIRE -48 144 -80 144
WIRE 32 144 -48 144
WIRE 592 144 592 -272
WIRE 592 144 272 144
WIRE -608 192 -608 16
WIRE -48 192 -48 144
WIRE -48 192 -608 192
WIRE 32 192 -48 192
WIRE 544 192 272 192
WIRE 592 192 592 144
WIRE 720 224 720 96
WIRE 32 240 -352 240
WIRE 352 240 272 240
WIRE -608 256 -608 192
WIRE -352 288 -352 240
WIRE 32 288 -352 288
WIRE 352 288 272 288
WIRE 32 336 -240 336
WIRE 432 336 272 336
WIRE -240 368 -240 336
WIRE -608 480 -608 336
WIRE -352 480 -352 288
WIRE -240 480 -240 448
WIRE 432 480 432 336
WIRE 544 480 544 192
WIRE 592 480 592 256
WIRE 720 480 720 288
WIRE 832 480 832 208
WIRE 976 480 976 128
FLAG -464 16 0
FLAG -304 128 0
FLAG -224 128 0
FLAG -608 480 0
FLAG -80 144 COMP
FLAG 592 480 0
FLAG 352 240 SRA
FLAG 352 288 SRB
FLAG 544 480 0
FLAG 432 480 0
FLAG -240 480 0
FLAG -352 480 0
FLAG 352 -48 OUTA
FLAG 352 -96 OUTB
FLAG 976 480 0
FLAG 352 -144 SYNC
FLAG 832 480 0
FLAG 720 480 0
FLAG 448 96 SS
FLAG -80 -144 IN
FLAG -80 -48 VLDO
SYMBOL AutoGenerated\\TPS7H5001-SP_TRANS 144 16 R0
SYMATTR InstName U1
SYMBOL voltage -464 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL cap -320 -16 R0
SYMATTR InstName C1
SYMATTR Value 1�
SYMBOL res -624 -80 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res -624 240 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL cap 576 192 R0
SYMATTR InstName C2
SYMATTR Value 470n
SYMBOL res -256 352 R0
SYMATTR InstName R3
SYMATTR Value 50k
SYMBOL res 960 32 R0
SYMATTR InstName R4
SYMATTR Value 500k
SYMBOL res 816 112 R0
SYMATTR InstName R5
SYMATTR Value 562k
SYMBOL cap 704 224 R0
SYMATTR InstName C3
SYMATTR Value 10p
TEXT -620 568 Left 2 !.tran 0.25m
TEXT -296 -496 Left 6 ;TPS7H5001 - SP Test Circuit
TEXT -1952 -312 Left 2 !* PSpice Model Editor - Version 17.4.0\n* TPS7H5001-SP\n*****************************************************************************\n* (C) Copyright 2021 Texas Instruments Incorporated. All rights reserved. \n*****************************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensors and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of \n** merchantability or fitness for a particular purpose. The model is\n** provided solely on an "as is" basis. The entire risk as to its quality\n** and performance is with the customer\n*****************************************************************************\n*\n* This model is subject to change without notice. Texas Instruments\n* Incorporated is not responsible for updating this model.\n*\n*****************************************************************************\n*\n** Released by: Texas Instruments Inc.\n* Part: TPS7H5001-SP\n* Date: 07NOV2022\n* Model Type: TRANSIENT \n* Simulator: PSPICE\n* Simulator Version: 17.4.0.s012\n* EVM Order Number: TPS7H5001EVM-CVAL\n* EVM Users Guide: SLVUBZ8\n* Datasheet: SLVSF07\n* Verified Topologies: Push-Pull, Buck, and Flyback\n* Model Version: RevC\n*\n*****************************************************************************\n*\n* Updates:\n*\n* RevA\n* 1. Moved subcircuit models into the main model\n*\n* RevB\n* 1. Fixed bug in blanking signal\n* 2. Updated component used for blanking reset\n* 3. Improved access to internal device parameters\n*\n* RevC\n* 1. Fixed RevB bug\n*\n*****************************************************************************\n*\n* Model Usage Notes:\n*\n* 1. These features have not been modeled:\n* - Fault delay\n* - Thermal shutdown\n* 2. Max step size of 20n is required for valid simulation results.\n*\n*****************************************************************************\n*$\n.SUBCKT TPS7H5001-SP_TRANS VIN EN VLDO DCL HICC FAULT COMP VSENSE SP PS LEB SYNC OUTB OUTA RT RSC SS REFCAP CS_ILIM SRA SRB AVSS\n+ PARAMS: EA_gm=1800u SS_thresh=1 I_ss=2.7u \nX_U112 RES_OUTB_PLS_B EN_FROM_HICC N16663350 AND2_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U99 N16662660 RES_OUTB_PLS N16662666 AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U79 DIS_FROM_HICC N16661660 N16661600 NOR2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nC_C_SP 0 SP 1f IC=0 TC=0,0 \nX_U77 P2 N16655464 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=8n\nX_U76 S2 N16655412 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=8n\nX_U66 S1 N16654302 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=8n\nR_R15 DCL N16642816 500k TC=0,0 \nE_E3 N16640395 0 N16640389 VSENSE 1\nE_LIMIT1 N16636926 0 VALUE {LIMIT(V(N16636920),-1m,1m)}\nR_R9 REFCAP N16635331 998.37 TC=0,0 \nX_U13 PWM_OUT N16637650 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U10 N16637752 N16637782 N16637790 BLANK_CS DIG_HI EN_FROM_HICC\n+ DFFSBRB_SHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_H2 N16639238 N16639306 N16639244 0 TPS7H5001-SP_TRANS_H2 \nR_R16 CS_ILIM N16643855 1.667k TC=0,0 \nX_U47 BLANK N16649561 SWITCH_CLOCK_PRE N16649565 AND3_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U48 DCL_HI DCL_HIZ N16649561 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_H5 N16649897 N16650431 N16650417 0 TPS7H5001-SP_TRANS_H5 \nX_U97 DIS_FROM_HICC N16662666 N16662578 NOR2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U83 DCL_HI RES_P_O BLANK_INT_B N16661924 AND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nE_ABM68 PS_OPEN 0 VALUE { IF( V(N16655582) > 208m, 0, 1) }\nX_U73 P2 N16655326 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=1n\nE_ABM10 N16655074 0 VALUE { IF( V(N16654790) > 1, 1, 0) }\nE_MUX3 S2_PS 0 VALUE { IF( V(PS_OPEN) < 0.5, \n+ V(N16654960), V(N16655086)) }\nX_U67 P1 N16654356 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=8n\nX_U61 N16653960 N16653966 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\nE_ABM60 N16653620 0 VALUE { V(REFCAP) }\nX_U58 N16653604 VLDO DCLAMP \nX_U38 HICC_OVER_1 N16647101 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM6 N16643158 0 VALUE { IF(V(dcl_0) < 0.5, \n+ V(DCL_CLOCK), V(VLDO)) }\nR_R13 N16642674 VLDO 500k TC=0,0 \nX_S3 BLANK_CS 0 N16636974 0 TPS7H5001-SP_TRANS_S3 \nR_R10 RT N16639306 19.7k TC=0,0 \nX_U16 N16639564 DIS_LOGIC OFF OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM50 PWM_COMP_OUT 0 VALUE { IF( V(HALF-COMP_M_SLOPE) > V(N16643805)\n+ , \n+ 1, 0) }\nE_ABM56 N16649867 0 VALUE { V(REFCAP) }\nX_U100 RES_OUTB_PLS RES_OUTB_PLS_B RES_OUTB DIG_HI N16662578 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U94 RES_OUTA_PLS_B EN_FROM_HICC N16662438 AND2_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U81 RES_OUTA_PLS RES_OUTA_PLS_B RES_OUTA DIG_HI N16661600 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nC_C14 0 N16654732 1.015p TC=0,0 \nE_MUX4 P2_SP 0 VALUE { IF( V(SP_OPEN) < 0.5, \n+ V(N16655080), V(N16655112)) }\nE_ABM66 SR2 0 VALUE { V(S2_PS) }\nG_G7 VLDO N16654732 N16654636 0 1\nX_U68 N16654732 VLDO DCLAMP \nX_S14 N16654084 0 N16653604 0 TPS7H5001-SP_TRANS_S14 \nG_G5 VLDO N16653604 N16653508 0 1\nX_U35 DISCHARGE_B CHARGE HICC_CHARGE AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U33 0 N16646553 DCLAMP \nX_S11 N16646521 0 HICC N16646553 TPS7H5001-SP_TRANS_S11 \nX_S10 HICC_CHARGE 0 N16646217 HICC TPS7H5001-SP_TRANS_S10 \nX_U17 COMP VLDO DCLAMP \nV_V1 N16635049 0 1\nV_V7 N16635859 0 1.5\nX_U42 BLANK NOT_BLANK N16649359 DIG_HI N16649275 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN_BLANK PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U55 PSP_DEL N16650133 BLANK_S OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U106 DCL_HIZ N16663086 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U89 SWITCH_CLOCK DCL_LO N16662122 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM67 OUT2 0 VALUE { V(P2_SP) }\nE_LIMIT8 N16654750 0 VALUE {LIMIT(V(N16654744),-1m,1m)}\nE_ABM5 DCL_LO 0 VALUE { IF(V(DCL_1) < 0.5, 1, 0) }\nE_ABM3 VLDO 0 VALUE { V(N16634959) }\nX_S1 N16634959 0 N16635049 N16635147 TPS7H5001-SP_TRANS_S1 \nR_R6 REFCAP N16635269 1 TC=0,0 \nE_ABM2 BANDGAP_REF 0 VALUE { V(N16635331) }\nX_U14 OSC N16639268 VCO_SQR PARAMS: Fcenter=2.00e+006 Frange=2.00e+006\n+ Vmin=0.0000e+000 Vmax=4MEG phase=0\nX_U114 P2 N16663504 S2 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U111 N16663314 SKIP_PULSE_B N16663320 AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nE_ABM65 N16654954 0 VALUE { IF( V(N16654732) > 1, 1, 0) }\nX_H8 N16653574 N16654702 N16654630 0 TPS7H5001-SP_TRANS_H8 \nX_U62 S1 N16654084 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=1n\nE_LIMIT6 N16653632 0 VALUE {LIMIT(V(N16653626),-1m,1m)}\nX_H6 N16653496 N16653574 N16653502 0 TPS7H5001-SP_TRANS_H6 \nE_ABM59 N16653496 0 VALUE { V(REFCAP) }\nX_U39 CHARGE N16647239 OCP_OUT DIG_HI N16647233 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U29 N16646217 VLDO DCLAMP \nE_ABM46 DCL_0 0 VALUE { IF(V(N16642770) > 1.5, 1, 0) }\nE_ABM29 N16638233 0 VALUE { IF( V(OUT1) > 100m, 5, 0) }\nC_C1 N16634959 0 80u IC=0 \nX_U9 SKIP_PULSE N16637900 SWITCH_CLOCK_PRE SKIP_PULSE_PRE DIG_HI\n+ EN_FROM_HICC DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U46 SWITCH_CLOCK_PRE SWITCH_CLOCK BUF_DELAY_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5 DELAY=1n\nE_LIMIT4 N16649879 0 VALUE {LIMIT(V(N16649873),-1m,1m)}\nX_U54 OUT1 OUT2 PWM_INT OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nR_R17 LEB N16650431 9.484k TC=0,0 \nX_U92 SKIP_PULSE_B N16662432 N16662370 AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nE_ABM69 SP_OPEN 0 VALUE { IF( V(N16655688) > 208m, 0, 1) }\nE_ABM63 N16653960 0 VALUE { IF( V(N16653672) > 1, 1, 0) }\nE_MUX1 S1_PS 0 VALUE { IF( V(PS_OPEN) < 0.5, \n+ V(N16653842), V(N16653976)) }\nX_U27 EN_LOGIC N16645993 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nR_R14 0 N16642674 500k TC=0,0 \nX_H3 N16642764 N16642816 N16642770 N16642826 TPS7H5001-SP_TRANS_H3 \nC_C9 COMP 0 1f IC=0 \nE_ABM41 N16638351 0 VALUE { IF( V(OUT2) > 100m, 5, 0) }\nG_G1 N16635859 SS N16635985 0 {I_SS}\nC_C8 SS 0 1f IC=0 \nX_S8 BLANK_CS 0 N16643855 0 TPS7H5001-SP_TRANS_S8 \nV_V13 N16643975 0 1.05\nX_U51 N16649667 PWM_INT BLANK_CS NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U110 N16663314 N16663356 SWITCH_CLOCK_B DIG_HI N16663350 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U87 BLANK_INT BLANK_INT_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U86 N16661924 RES_OUTA_PRE N16661590 RES_OUTA OR3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U75 P2 N16655464 N16655112 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U64 S1 N16654302 N16653976 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM62 SR1 0 VALUE { V(S1_PS) }\nX_U30 HICC_CHARGE N16646521 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nR_R3 N16638351 OUTB 15 TC=0,0 \nR_R5 N16634959 N16634953 250m TC=0,0 \nX_U2 SS_PD N16635995 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_ABM43 OSC 0 VALUE { IF( V(off) <0.5, 2* LIMIT( 112000/ ( {V(REFCAP)}/\n+ (V(N16639244)*1k) )*1k, 100k, 2MEG), 0) }\nX_U56 P1_SP P2_SP N16650125 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U104 SWITCH_CLOCK_B DIG_HI N16662988 AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U102 SWITCH_CLOCK SWITCH_CLOCK_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U78 RES_P_O DCL_HIZ BLANK_INT_B N16661590 AND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_S16 N16655194 0 N16654732 0 TPS7H5001-SP_TRANS_S16 \nE_LIMIT7 N16654636 0 VALUE {LIMIT(V(N16654630),-1m,1m)}\nG_G6 VLDO N16653672 N16653632 0 1\nE_LIMIT5 N16653508 0 VALUE {LIMIT(V(N16653502),-1m,1m)}\nE_E4 N16640407 0 N16640401 0 {EA_gm}\nR_R1 N16638233 OUTA 15 TC=0,0 \nE_ABM13 N16639274 0 VALUE { LIMIT( V(N16639268), 1, 0) * 5 }\nX_U22 PWM_COMP_OUT EN_FROM_HICC PWM_OUT AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nE_ABM51 N16643961 0 VALUE { IF( V(N16643855) > V(N16643975) , \n+ 1, 0) }\nX_U43 SYS_CLOCK SWITCH_CLOCK_PRE DCL_CLOCK OR2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nC_C12 0 N16649927 1.011p TC=0,0 \nX_U98 OUT2 N16662660 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U84 N16661856 OCP_OUT RES_P_O OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nR_R18 PS N16655664 8.858k TC=0,0 \nX_H11 N16654760 N16655714 N16655688 0 TPS7H5001-SP_TRANS_H11 \nX_H10 N16654702 N16655664 N16655582 0 TPS7H5001-SP_TRANS_H10 \nE_ABM61 N16653836 0 VALUE { IF( V(N16653604) > 1, 1, 0) }\nX_S12 HICC_PD 0 HICC 0 TPS7H5001-SP_TRANS_S12 \nV_V2 N16642826 0 1\nE_ABM1 HALF-COMP_M_SLOPE 0 VALUE { ( V(N16636974)*-4.2657+ \n+ V(COMP)*0.5 ) }\nX_U11 DCL_CLOCK N16637790 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM44 RT_PRESENT 0 VALUE { IF(V(N16639244) > 60.65n, 1, 0) }\nC_C_RT 0 RT 1f IC=0 TC=0,0 \nX_U20 VLDO_GOOD N16641690 N16641548 DIS_LOGIC NAND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_S7 FAULT 0 N16641852 N16641886 TPS7H5001-SP_TRANS_S7 \nX_U21 N16641852 N16641690 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U24 BLANK_CS N16643985 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U49 N16649565 N16649681 BLANK_INT OR2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nC_C_LEB 0 LEB 1f IC=0 TC=0,0 \nX_U90 SKIP_PULSE SKIP_PULSE_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U80 RES_OUTA_PLS N16661838 N16661660 AND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U72 S2 N16655194 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=1n\nX_U70 N16654954 N16654960 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\nX_H7 N16653620 N16653642 N16653626 0 TPS7H5001-SP_TRANS_H7 \nX_U34 DISCHARGE DISCHARGE_B N16646929 DIG_HI HICC_OVER_0P3 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_S9 HICC_TRIG 0 VLDO HICC TPS7H5001-SP_TRANS_S9 \nI_I1 VLDO N16646217 DC 80u \nC_C10 0 DCL 1f TC=0,0 \nE_ABM45 N16640389 0 VALUE { IF( V(SS) < V(BANDGAP_REF), \n+ V(SS), V(BANDGAP_REF) ) }\nC_C2 0 N16636974 15.5p IC=0 TC=0,0 \nE_E1 N16636914 0 REFCAP 0 1\nV_V11 DIG_HI 0 5\nR_R8 N16635331 0 1k TC=0,0 \nX_U3 EN_LOGIC N16635995 N16635985 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM8 SS_DONE 0 VALUE { IF((V(SS) > {SS_thresh}), 1, 0) }\nR_R11 0 N16641548 1 TC=0,0 \nR_R12 0 N16641852 1 TC=0,0 \nX_U45 SWITCH_CLOCK_PRE N16649203 SYS_CLOCK N16649203 EN_LOGIC DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_ABM57 N16650075 0 VALUE { IF( V(N16649927) > 1, 1, 0) }\nX_S13 N16650133 0 N16649927 0 TPS7H5001-SP_TRANS_S13 \nX_U107 N16663086 N16663130 EN_FROM_HICC N16663136 AND3_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U71 N16655074 N16655080 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\nX_U69 N16654790 VLDO DCLAMP \nC_C3 0 N16653672 1.015p TC=0,0 \nE_MUX2 P1_SP 0 VALUE { IF( V(SP_OPEN) < 0.5, \n+ V(N16653966), V(N16654002)) }\nX_U59 N16653672 VLDO DCLAMP \nX_U28 DIS_FROM_HICC EN_FROM_HICC INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM52 SS_PD 0 VALUE { V(DIS_FROM_HICC) }\nE_LIMIT2 N16640401 0 VALUE {LIMIT(V(N16640395),-83m,83m)}\nR_R7 N16635147 0 1 TC=0,0 \nX_S2 N16636189 0 SS 0 TPS7H5001-SP_TRANS_S2 \nX_U12 N16637650 N16637752 BLANK_CS SKIP_PULSE_PRE AND3_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_E2 N16639238 0 REFCAP 0 1\nX_U6 SYNC N16639420 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_S6 EN 0 N16641548 N16641580 TPS7H5001-SP_TRANS_S6 \nV_V12 N16643805 N16643855 150m\nX_U23 N16643961 N16643985 OCP_OUT AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM58 LEB_OPEN 0 VALUE { IF( V(N16650417) > 208m, 0, 1) }\nX_U109 N16663136 N16663320 N16663068 P2 AND3_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U108 DCL_HI N16663130 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U103 RES_P_O N16662988 BLANK_INT_B N16662972 AND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U74 S2 N16655412 N16655086 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_S15 N16654216 0 N16653672 0 TPS7H5001-SP_TRANS_S15 \nE_ABM64 OUT1 0 VALUE { V(P1_SP) }\nX_U36 HICC_TRIG N16646929 HICC_OVER_0P6 DIG_HI N16647061 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nI_I2 N16646553 0 DC 1u \nE_ABM53 HICC_OVER_1 0 VALUE { IF( V(HICC)>1, 1, 0) }\nE_ABM48 DCL_1 0 VALUE { IF(V(N16642770) > 0.5, 1, 0) }\nE_TABLE2 N16635269 0 TABLE {V(N16634959)} 200mV 1mV \n+ 1.4V 1.225V \n+ 15.6V 1.23V\nE_ABM12 SYS_CLOCK 0 VALUE { IF(V(RT_present)>0.5, V(N16639274),\n+ V(N16639420) ) \n+ }\nX_U15 RT_PRESENT N16639564 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U52 N16649927 VLDO DCLAMP \nG_G4 VLDO N16649927 N16649879 0 1\nX_U95 P1 N16662560 S1 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U85 OUT1 N16661838 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_ABM7 DCL_MASK 0 VALUE { IF(V(dcl_1) < 0.5, \n+ V(SWITCH_CLOCK), V(N16643158)) }\nX_U18 0 COMP DCLAMP \nE_ABM42 N16638411 0 VALUE { IF( V(SR2) > 100m, 5, 0) }\nX_U5 N16636974 VLDO DCLAMP \nX_U4 N16635995 EN_LOGIC N16636189 NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U19 VLDO_GOOD N16641690 N16641548 EN_LOGIC AND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nR_R19 SP N16655714 8.858k TC=0,0 \nG_G8 VLDO N16654790 N16654750 0 1\nX_U63 P1 N16654216 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\n+ DELAY=1n\nX_U60 N16653836 N16653842 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\nE_ABM54 HICC_OVER_0P6 0 VALUE { IF( V(HICC)>0.6, 1, 0) }\nX_U26 HICC_ON N16645993 DIS_FROM_HICC OR2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nE_LIMIT3 N16640413 0 VALUE {LIMIT(V(N16640407),-190u,190u)}\nE_ABM40 N16638293 0 VALUE { IF( V(SR1) > 100m, 5, 0) }\nC_C11 0 N16643855 100f IC=0 TC=0,0 \nX_U53 DCL_LO BLANK N16649681 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_H4 N16649867 N16649897 N16649873 0 TPS7H5001-SP_TRANS_H4 \nX_U57 N16650125 N16650133 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U82 PWM_OUT N16661856 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nC_C13 0 N16653604 1.015p TC=0,0 \nX_U40 NOT_BLANK EN_LOGIC N16647233 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U32 OCP_OUT N16646713 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_ABM49 DCL_HIZ 0 VALUE { IF(V(DCL_1)*(1-V(DCL_0)) > 0.5, \n+ 1, 0) }\nX_S5 SS_PD 0 COMP 0 TPS7H5001-SP_TRANS_S5 \nG_G3 VLDO COMP N16640413 0 1\nG_G2 VLDO N16636974 N16636926 0 1\nE_TABLE1 N16634953 0 TABLE {V(VIN)} 200mV 1mV \n+ 5.1V 5V \n+ 15.6V 5.002V\nX_U1 SS N16635859 DCLAMP \nX_S4 RT_PRESENT 0 N16639274 SYNC TPS7H5001-SP_TRANS_S4 \nV_V5 N16641580 0 1\nV_V4 N16641886 0 1\nX_U113 SS_DONE EN_FROM_HICC DCL_LO N16663504 NAND3_BASIC_GEN PARAMS: \n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U105 DCL_MASK N16663068 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U101 DCL_HIZ N16662972 DCL_HI RES_OUTB OR3_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U93 N16662432 N16662444 SWITCH_CLOCK DIG_HI N16662438 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U88 BLANK_INT_B N16662122 RES_P_O RES_OUTA_PRE AND3_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5\nC_C4 0 N16654790 1.015p TC=0,0 \nX_H9 N16653642 N16654760 N16654744 0 TPS7H5001-SP_TRANS_H9 \nX_U31 HICC_PD N16646719 DISCHARGE_B DIG_HI N16646713 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U25 HICC_ON N16645989 HICC_OVER_0P6 DIG_HI HICC_OVER_0P3 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_E5 N16642764 0 N16642674 0 1\nR_R4 N16638411 SRB 15 TC=0,0 \nX_U50 BLANK_INT N16649667 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U96 SS_DONE EN_FROM_HICC N16662560 NAND2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U91 EN_FROM_HICC N16662370 DCL_MASK P1 AND3_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nC_C_PS 0 PS 1f IC=0 TC=0,0 \nX_S17 N16655326 0 N16654790 0 TPS7H5001-SP_TRANS_S17 \nX_U65 P1 N16654356 N16654002 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nX_U37 EN_LOGIC N16647101 N16647061 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5\nE_ABM55 HICC_OVER_0P3 0 VALUE { IF( V(HICC)>0.3, 1, 0) }\nE_ABM47 DCL_HI 0 VALUE { IF(V(DCL_0)*V(DCL_1) > 0.5, \n+ 1, 0) }\nR_R2 N16638293 SRA 15 TC=0,0 \nX_H1 N16636914 RSC N16636920 0 TPS7H5001-SP_TRANS_H1 \nE_ABM4 VLDO_GOOD 0 VALUE { IF(V(N16635147)>0.5, 1, 0) }\nX_U44 BLANK_RESET DIS_LOGIC N16649275 NOR2_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nE_MUX PSP_DEL 0 VALUE { IF( V(LEB_OPEN) < 0.5, \n+ V(N16650075), V(N16650125)) }\nX_U115 BLANK_RESET N16685413 PSP_DEL DIG_HI N16685409 DIG_HI\n+ DFFSBRB_RHPBASIC_GEN_BLANK PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U116 PSP_DEL N16685409 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\nX_U117 SYS_CLOCK N16649359 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=0.5 DELAY=20n\n.ENDS TPS7H5001-SP_TRANS\n*$\n.subckt TPS7H5001-SP_TRANS_H2 1 2 3 4 \nH_H2 3 4 VH_H2 1\nVH_H2 1 2 0V\n.ends TPS7H5001-SP_TRANS_H2\n \n.subckt TPS7H5001-SP_TRANS_H5 1 2 3 4 \nH_H5 3 4 VH_H5 100k\nVH_H5 1 2 0V\n.ends TPS7H5001-SP_TRANS_H5\n \n.subckt TPS7H5001-SP_TRANS_S3 1 2 3 4 \nS_S3 3 4 1 2 _S3\nRS_S3 1 2 1G\n.MODEL _S3 VSWITCH Roff=1G Ron=1 Voff=0.2 Von=0.8\n.ends TPS7H5001-SP_TRANS_S3\n \n.subckt TPS7H5001-SP_TRANS_S14 1 2 3 4 \nS_S14 3 4 1 2 _S14\nRS_S14 1 2 1G\n.MODEL _S14 VSWITCH Roff=1G Ron=1.0 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S14\n \n.subckt TPS7H5001-SP_TRANS_S11 1 2 3 4 \nS_S11 3 4 1 2 _S11\nRS_S11 1 2 1G\n.MODEL _S11 VSWITCH Roff=1G Ron=100 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S11\n \n.subckt TPS7H5001-SP_TRANS_S10 1 2 3 4 \nS_S10 3 4 1 2 _S10\nRS_S10 1 2 1G\n.MODEL _S10 VSWITCH Roff=1G Ron=100 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S10\n \n.subckt TPS7H5001-SP_TRANS_S1 1 2 3 4 \nS_S1 3 4 1 2 _S1\nRS_S1 1 2 1G\n.MODEL _S1 VSWITCH Roff=1G Ron=1f VH=0.075 VT=3.475 TD=0\n.ends TPS7H5001-SP_TRANS_S1\n \n.subckt TPS7H5001-SP_TRANS_H8 1 2 3 4 \nH_H8 3 4 VH_H8 1\nVH_H8 1 2 0V\n.ends TPS7H5001-SP_TRANS_H8\n \n.subckt TPS7H5001-SP_TRANS_H6 1 2 3 4 \nH_H6 3 4 VH_H6 1\nVH_H6 1 2 0V\n.ends TPS7H5001-SP_TRANS_H6\n \n.subckt TPS7H5001-SP_TRANS_H3 1 2 3 4 \nH_H3 3 4 VH_H3 -200k\nVH_H3 1 2 0V\n.ends TPS7H5001-SP_TRANS_H3\n \n.subckt TPS7H5001-SP_TRANS_S8 1 2 3 4 \nS_S8 3 4 1 2 _S8\nRS_S8 1 2 1G\n.MODEL _S8 VSWITCH Roff=100MEG Ron=100m Voff=0 Von=1\n.ends TPS7H5001-SP_TRANS_S8\n \n.subckt TPS7H5001-SP_TRANS_S16 1 2 3 4 \nS_S16 3 4 1 2 _S16\nRS_S16 1 2 1G\n.MODEL _S16 VSWITCH Roff=1G Ron=1.0 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S16\n \n.subckt TPS7H5001-SP_TRANS_H11 1 2 3 4 \nH_H11 3 4 VH_H11 100k\nVH_H11 1 2 0V\n.ends TPS7H5001-SP_TRANS_H11\n \n.subckt TPS7H5001-SP_TRANS_H10 1 2 3 4 \nH_H10 3 4 VH_H10 100k\nVH_H10 1 2 0V\n.ends TPS7H5001-SP_TRANS_H10\n \n.subckt TPS7H5001-SP_TRANS_S12 1 2 3 4 \nS_S12 3 4 1 2 _S12\nRS_S12 1 2 1G\n.MODEL _S12 VSWITCH Roff=1G Ron=100 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S12\n \n.subckt TPS7H5001-SP_TRANS_S7 1 2 3 4 \nS_S7 3 4 1 2 _S7\nRS_S7 1 2 1G\n.MODEL _S7 VSWITCH Roff=1e6 Ron=1f VH=0.05 VT=0.55 TD=10n\n.ends TPS7H5001-SP_TRANS_S7\n \n.subckt TPS7H5001-SP_TRANS_H7 1 2 3 4 \nH_H7 3 4 VH_H7 1\nVH_H7 1 2 0V\n.ends TPS7H5001-SP_TRANS_H7\n \n.subckt TPS7H5001-SP_TRANS_S9 1 2 3 4 \nS_S9 3 4 1 2 _S9\nRS_S9 1 2 1G\n.MODEL _S9 VSWITCH Roff=1G Ron=4k Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S9\n \n.subckt TPS7H5001-SP_TRANS_S13 1 2 3 4 \nS_S13 3 4 1 2 _S13\nRS_S13 1 2 1G\n.MODEL _S13 VSWITCH Roff=100MEG Ron=1.0 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S13\n \n.subckt TPS7H5001-SP_TRANS_S2 1 2 3 4 \nS_S2 3 4 1 2 _S2\nRS_S2 1 2 1G\n.MODEL _S2 VSWITCH Roff=100MEG Ron=250 VH=0 VT=0.5 TD=10n\n.ends TPS7H5001-SP_TRANS_S2\n \n.subckt TPS7H5001-SP_TRANS_S6 1 2 3 4 \nS_S6 3 4 1 2 _S6\nRS_S6 1 2 1G\n.MODEL _S6 VSWITCH Roff=1e6 Ron=1f VH=0.05 VT=0.55 TD=10n\n.ends TPS7H5001-SP_TRANS_S6\n \n.subckt TPS7H5001-SP_TRANS_S15 1 2 3 4 \nS_S15 3 4 1 2 _S15\nRS_S15 1 2 1G\n.MODEL _S15 VSWITCH Roff=1G Ron=1.0 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S15\n \n.subckt TPS7H5001-SP_TRANS_H4 1 2 3 4 \nH_H4 3 4 VH_H4 1\nVH_H4 1 2 0V\n.ends TPS7H5001-SP_TRANS_H4\n \n.subckt TPS7H5001-SP_TRANS_S5 1 2 3 4 \nS_S5 3 4 1 2 _S5\nRS_S5 1 2 1G\n.MODEL _S5 VSWITCH Roff=7MEG Ron=10 Voff=0 Von=1\n.ends TPS7H5001-SP_TRANS_S5\n \n.subckt TPS7H5001-SP_TRANS_S4 1 2 3 4 \nS_S4 3 4 1 2 _S4\nRS_S4 1 2 1G\n.MODEL _S4 VSWITCH Roff=1G Ron=1f Voff=0 Von=1\n.ends TPS7H5001-SP_TRANS_S4\n \n.subckt TPS7H5001-SP_TRANS_H9 1 2 3 4 \nH_H9 3 4 VH_H9 1\nVH_H9 1 2 0V\n.ends TPS7H5001-SP_TRANS_H9\n \n.subckt TPS7H5001-SP_TRANS_S17 1 2 3 4 \nS_S17 3 4 1 2 _S17\nRS_S17 1 2 1G\n.MODEL _S17 VSWITCH Roff=1G Ron=1.0 Voff=0.0V Von=1.0V\n.ends TPS7H5001-SP_TRANS_S17\n \n.subckt TPS7H5001-SP_TRANS_H1 1 2 3 4 \nH_H1 3 4 VH_H1 100m\nVH_H1 1 2 0V\n.ends TPS7H5001-SP_TRANS_H1\n*****************************************************************************\n*$\n.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND2_BASIC_GEN\n*$\n.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH} &\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND3_BASIC_GEN\n*$\n.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NAND2_BASIC_GEN\n*$\n.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH} &\n+ V(C) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NAND3_BASIC_GEN\n*$\n.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR2_BASIC_GEN\n*$\n.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH} |\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR3_BASIC_GEN\n*$\n.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NOR2_BASIC_GEN\n*$\n.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS INV_BASIC_GEN\n*$\n.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT1 YINT2 1\nCINT YINT2 0 {DELAY*1.3}\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \n+ {VSS},{VDD})}}\nRINT2 YINT3 Y 1\nCINT2 Y 0 1n\n.ENDS INV_DELAY_BASIC_GEN\n*$\n.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT1 YINT2 1\nCINT YINT2 0 {DELAY*1.44}\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT2 YINT3 Y 1\nCINT2 Y 0 1n\n.ENDS BUF_DELAY_BASIC_GEN\n*$\n.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \n***Set has higher priority in this\n** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations\n**Faster flip-flops require a a smaller time step to simulate\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} \nGQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, \n+ IF(V(D)> {VTHRESH},5,-5),0)))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D1\nV1 MY5 0 5\nD_D11 0 Qint D_D1 \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr Qb 1 \nCdummy1 Q 0 1nF \nCdummy2 QB 0 1nF \n.IC V(Qint) {VSS}\n.ENDS DFFSBRB_RHPBASIC_GEN\n*$\n.subckt DCLAMP A C\nG1 A C TABLE { V(A, C) } ( (-1,-1n)(0,0)(1m,1) (2m,10) (3m,1000) )\n.ends DCLAMP \n*$\n.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.001 N=.1 )\n*$\n.SUBCKT DFFSBRB_RHPBASIC_GEN_BLANK Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \n**Faster flip-flops require a a smaller time step to simulate\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 10n\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} \nGQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, \n+ IF(V(D)> {VTHRESH},5,-5),0)))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D1\nV1 MY5 0 5\nD_D11 0 Qint D_D1 \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 1p\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr Qb 1 \nCdummy1 Q 0 1nF \nCdummy2 QB 0 1nF \n.IC V(Qint) {VSS}\n.ENDS DFFSBRB_RHPBASIC_GEN_BLANK\n*$\n.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \n***Set has higher priority in this\n** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations\n**Faster flip-flops require a a smaller time step to simulate\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\nGQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, \n+ IF(V(D)> {VTHRESH},5,-5),0)))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D1\nV1 MY5 0 {VDD}\nD_D11 MYVSS Qint D_D1\nV2 MYVSS 0 {VSS} \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr Qb 1 \nCdummy1 Q 0 1nF \nCdummy2 QB 0 1nF \n.IC V(Qint) {VSS}\n.ENDS DFFSBRB_SHPBASIC_GEN\n*$\n.subckt VCO_SQR in out PARAMS: Fcenter=2.00e+006 Frange=2.00e+006 Vmin=0 Vmax=4MEG phase=0 \nRin in 0 1G\nRtable table 0 1G\nEtable table 0 Value {Table(V(in),Vmin,-1,Vmax,1)}\nEsin sine 0 \n+Value {sin(6.28318*(Fcenter*time+Frange*SDT(V(table)))+phase*(3.14159/180))}\nEsqr out 0 table {V(sine)} (0,0) (1n,1)\n.ends vco_sqr\n*$
