TL494: TL494 BOOST CONVERTER ERROR

jwy0511

Part Number: TL494
Other Parts Discussed in Thread: CSD19534KCS

The above is a circuit diagram of the BOOST CONVERTER using the designed TL494.

1. Operational problems
1.1 When power is applied, MOSFET is damaged, S and D are shorted, and power supply CC operation
1.2 Same phenomenon with SMD type NVMFS5H663NL MOSFET

2. It is judged that the specifications of the elements are not lacking, is there any problem with the circuit problem with the circuit?

3. Also, Inductor L1 is built with IDC 30A at 68uH, R6,R18 uses current sensing resistance from GMR320HJAAFD5L00, F1 to F5 used NFM41PC155B1H3 EMI filter.

4. Designing a High Power, High Efficiency Boost Converter using TL494 (circuitdigest.com) I referred to the link.

over 2 years ago

0 JCHK over 2 years ago

TI__Guru 50190 points

Hi,

Let me try to answer your questions:

1. Are you able to use an oscilloscope to probe the 24V rail and VDS of the FET when power is plugged in? The CSD19534KCS is a 100V-rated FET, the NVMFS5H663NL is only a 60V-rated FET. The design you refer to uses a 200V-rated FET.

2. You have a lot of capacitance and nothing to limit the inrush current. The LC ringing might be larger than you expect. TI has inrush or hot swap controllers which can help minimize inrush.

3. I am not seeing GMR320HJAAFD5L00 or the EMI stage, but R6 and R18 can only sense the IDS of Q1.

I hope this gives you some ideas.

0 jwy0511 over 2 years ago in reply to JCHK

Prodigy 60 points

Thank you for your answer.
Use input: 24 VDC, output: 48 VDC/Rated Current: 22A, Maximum Current: 30A.

1. Is there a standard for selecting Vds of FET?
2. What is the rating standard for Id of the FET to be selected?

0 JCHK over 2 years ago in reply to jwy0511

TI__Guru 50190 points

Hi,

I am not sure if there is an official standard for selecting Vds of a FET, but normally an 80% derating factor is what people design with. For example, if you expect to see voltage spikes up to 100V either as a result of inrush or input voltage line transients, a common practice is to make sure the FET can at least handle 120V.

The same is true for the Ids of the FET. If you assume a peak current of 30A at the output, assuming perfect efficiency that would translate to more than double the current from the input supply. So if we assume the peak input current is 80A, then using this same rule of thumb you may want to select a FET that can handle 100A.

Another spec to look for is to make sure that the FET is avalanche rated or can handle the high dVds/dt it will be seeing in this application.

I hope this helps.

0 jwy0511 over 2 years ago in reply to JCHK

Prodigy 60 points

Questions
1. So you see in the circuit diagram above that a spike of up to about 150V or more can occur as a result of an inrush or input voltage line transient, but why did you think so?

2. To solve the problem, I experimented by lowering the gate voltage of Q1 by adjusting the low voltage (about 5-7V) and R4 and R5 in Vin.

However, even if the gate voltage of the FET exceeds about 2~4V, the parts in the PCB immediately make a sound of wearing damage.

The Vgs of Q1 is 20V and I don't understand why such a problem occurs.

0 JCHK over 2 years ago in reply to jwy0511

TI__Guru 50190 points

Hi,

For question #1. I am not sure how high the voltage spike can be. Have you tried measuring it with an oscilloscope?

For question #2. I think you may need to find a FET that can both handle whatever voltage spikes it may be seeing and the peak current. You may also want to look at L1. I just realized you have a 30A inductor where the peak inductor current can easily exceed 44A. This may be saturating.

0 jwy0511 over 2 years ago in reply to JCHK

Prodigy 60 points

1. I think inductor A capacity is irrelevant because the current experiment did not apply the load itself, and only voltage was applied.

2. It is difficult to measure Vgs due to CC caused by short circuit as soon as power is applied, but the same phenomenon is repeated even when using FET rated at 250V 90A.

3. What should be the proper duty ratio and the voltage going into the FET Gate pin?
In the current experiment, the switching frequency is 100 kHz, the duty ratio is approximately 41%, and the voltage is 8 V.

The voltage and duty ratios required to be applied to the appropriate FET Gate pin for the circuit to operate properly are poor. Also, I would appreciate it if you could answer what the duty fee is determined by.

0 JCHK over 2 years ago in reply to jwy0511

TI__Guru 50190 points

Hi,

If a short circuit occurs the moment power is supplied. I would limit the power supply to a few mA and see where the current is flowing. It sounds like there is an issue with the test setup.

Another question is what is going on with this part of the circuit?

I see you have a lot of capacitance on the Vref pin. This seems excessive. The device will thermally shutdown if too much current is pulled out of the Vref pin. This pin is only capable of sourcing up to 10mA for external bias.

0 jwy0511 over 2 years ago in reply to JCHK

Prodigy 60 points

Thank you for your answer. In order to prevent an inrush current, the above circuit is designed to take approximately 4V of the DTC pin at the beginning of the power application and 0.45V of the DTC pin.

All capacitors connected to the REF pin, including the above circuit, have been removed and tested, but there is no difference.

Most importantly, the constant voltage of TL494 is not operating normally.

1. However, if the gate voltage is large when the load after the FET is connected, the CC operation will occur and the circuit will be damaged.

2. Even if you adjust the resistance value connected to the gate to match the gate voltage that does not work CC, the design value of Vout does not appear.

2.1 If you do not connect a post-FET load to TL494, a normal waveform of the square wave will appear. Below is an example picture (Vp-p values may vary depending on tuning)

2.2 However, if the load is connected after the FET terminal, the gate waveform is crushed as shown below, and the waveform of the inductor L also has an incorrect duty ratio of 96%.

So of course there is no change in constant voltage output due to variable resistance. This is not a normal PWM operation.

3. Crucially, if pin 2 has 2.5V, pin 1 also has 2.5V (using the characteristics of the operational amplifier), Vout should have a constant voltage operation of about 40V~50V depending on the resistance values of RV1, R7, and R10, and pin 2 does not have the same voltage as pin 1.

So of course there is no change in constant voltage output due to variable resistance. This is not a normal PWM operation. And the duty ratio or Vp-p of the gate end of the FET is automatically adjusted to become a constant voltage, and I think it is not appropriate to adjust the constant voltage of the gate that is not arbitrarily shorted.

TL494 I would appreciate it if you could help the PWM work normally.