Other Parts Discussed in Thread: LP87642Q1EVM
I am using the LP87642Q1EVM. I have the WD_ERROR trigger taking the PFSM to a WD_ERROR state, where I am forcing nRSTOUT to be 1'b0. My intention is for an external processor to write 1'b1 to bit 0 in MISC_CTRL register so that nRSTOUT is de asserted.. For this I am making SREG_0 = 0x81 in the power sequence ACT2WDE. My idea is that the state machine will stay in WD_ERROR and when MISC_TRL register bit 0 is set, the state machine will transition to active state. I do see that the statemachine enters WD_ERROR for the first time when the watchdog error occurs. Then I write 1'b1 to MISC_CTRL bit 0. I do see that the nRSTOUT get de asserted. But the state does not seem to go to ACTIVE state as the WD_ERROR_RISE trigger is not asserting the nRSTOUT again (LED does not glow).
How can i make this happen ?