Hi TI Experts,
I have 3 questions about the Efficiency around the VG pin of the TPS54A20.
1. It says that applying 5V to the VG+ pin turns off the internal LDO, which improves efficiency, but what is the loss of this LDO?
2. If a DCDC that steps down 12V to 5V is applied to VG+, does that mean that the difference in efficiency between the internal LDO and the prepared DCDC will improve efficiency?
3. It seems that the lower the supply voltage to VG+, the lower the loss. What is the minimum rating for VG+? (Is it possible to calculate the value of the current flowing through the VG pin when the voltage is changed?)
Thank you for your confirmation.