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# CSD18531Q5A: SOA operating limits and Reliability

Part Number: CSD18531Q5A
Other Parts Discussed in Thread: CSD18532Q5B

Hi,

I am using MOSFET part – CSD18531Q5A. The MOSFET is used as Ideal diode & as a Load switch.

The maximum steady state current is 16A and maximum inrush current can be 42A. The below current waveform tells the inrush current experienced by MOSFET(Yellow Signal).  I have plotted the SOA graph, it looks to be with in the limits of MOSFET. This is not a recurring inrush current nor a switching MOSFET. We are looking for a reliability of 7000 cycles. Do you see any concerns in using the MOSFET under these conditions? Can you also share the derated SOA for a case temperature of 75degC?

• Hello Niranjan,

Thanks for your interest in TI FETs. The inrush event lasts about 1ms. As a worst case approximation, we can assume square voltage and current pulses. For a 1ms square pulse at VDS = 8V, from the SOA graph in the datasheet, the drain current is approximately IDS = 70A. Using a linear approximation, the derated drain current at TC = 75°C can be calculated as follows:

IDS(TC=75°C) = 70A x (TJmax - TC)/(TJmax - 25°C) = 70A x (150°C - 75°C)/(150°C - 25°C) = 42A

Based on this, it should be OK to operate the FET under these conditions. Please see the app note at the link below. Since both the current and voltage are not square waveforms, you should have additional margin in your design. In the app note, you will see how to calculate the temperature derating and how to deal with non-square pulses by calculating an equivalent square pulse.The second link provides more details on how TI tests and specs SOA in our FET datasheets.

https://www.ti.com/lit/an/sluaao2/sluaao2.pdf

https://e2e.ti.com/blogs_/b/powerhouse/posts/understanding-mosfet-data-sheets-part-2-safe-operating-area-soa-graph

Best Regards,

John Wallace

TI FET Applications

• Hi John,

Based on this, it should be OK to operate the FET under these conditions. Please see the app note at the link below. Since both the current and voltage are not square waveforms, you should have additional margin in your design.

Considering its not a square pulse, do u mean that I have additional margin in my design?. Can the MOSFET withstand this inrush current can for 7000 times?

In general, is it okay to operate a MOSFET above the DC line but with in the limits of SOA line? For instance, lets say VDS is 10V and IDS is 1A recurring square pulses of 500uS, which is falling between DC and 10mS line. Is it okay for the MOSFET or is it being stressed?

Niranjan Pandian

• Hi Niranjan,

From my previous response, 70A SOA current for 8V/1ms is based on a square pulse of power. As described in the blog in my response, this is how TI performs SOA testing to failure on our FETs. The waveforms you provided are not square pulses and contain less energy. The app note I sent includes a method to estimate the equivalent square pulse width for non-square waveforms by equating the energy. Please see attached. I used linear approximations for the voltage and current waveforms, multiplied them to get power and integrated over the inrush time period to get the energy in the power pulse. Then I divided this by the peak power to get the equivalent square wave pulse width (585μs). Lastly, I estimated the SOA current (~90A) for the equivalent pulse width and derated for 75°C case temperature (53.8A). This is all described in the app note. As long as the operating conditions do not violate the SOA limit lines for a given pulse width, the FET should operate reliably for its lifetime. The CSD18531Q5A should have no problem operating under these conditions for 7000+ cycles. Let me know if you have any questions.

John

CSD18531Q5A SOA.pdf

• Hi John, Its gives a lot of clarity now. Thank you for taking your time and explaining it in detail.

• Hi John,

1. Is the SOA given in datasheet is de-rated graph or actual? If so, how much is it de-rated for?

2. Is there way provide heat sink for the MOSFET CSD18531Q5A? Can u suggest some mechanisms or part number?

Thank you & Regards,

Niranjan Pandian

• Hi Niranjan,

Thanks again for your interest in TI FETs. As explained in the blog I provided a link for in my earlier response, TI tests to failure and then derates by 30% to 40% for the datasheet SOA graph. For the CSD18531Q5A, the thermal instability region is derated by 30%. It is possible to heat sink these devices although the main path to remove heat from the package is thru the large thermal (drain) pad on the bottom of the device and into the PCB. By comparison, the max thermal resistance from junction-to-case on the bottom is 1°C/W and on the top of the package is approximately 15°C/W.There are many suppliers that make heat sinks for these types of devices. Here are some links:

https://www.boydcorp.com/thermal/air-cooling/heat-sinks.html

https://wakefieldthermal.com/thermal-solutions/air-cooled/

With 16A steady state current, the conduction loss in the CSD18531Q5A is about 2.1W assuming TJ = 125°C. That is within the capability of the package (~3W max) and should be OK. If the conduction loss is too high and the FET temperature is exceeding your requirements, then you can consider upgrading to a lower on resistance FET such as the CSD18532Q5B.This would reduce the conduction loss to 1.5W but is a higher cost device.

I am curious why you have chosen a 60V FET when it looks like your bus voltage is only 20V. You may be able to use a 40V device or even a 30V FET for this application. This could be more cost effective than a 60V device.

Thanks,

John

• Hi John,

Thank you for explaining in detail.

I have another doubt from the blog statement

"As a final guarantee of the reliability of our SOA curve, we de-rate each measured thermal runaway line anywhere from 30-40%, depending on how much part to part variation we see."

It mentions part to part variations, does it mean that,if i take batch of MOSFET, in some samples the SOA limit might be as low or high as 30%? or does it mean that on top of variations the de-rating is added?

Forgive my ignorance, appreciate your patience.

Niranjan Pandian.

• Hi Niranjan,

The reason we de-rate from the failure points is because there is part-to-part variation. I don't believe it is as high as 30%. I checked with a colleague who was directly involved with SOA testing and setting limits for the FET datasheets. He said that 30% was what the team felt comfortable with at the time. TI has multiple FET technologies and generations. He also told me that our 40V and 60V (including the CSD18531Q5A) were very consistent from part-to-part (~5%). This gives me high confidence that this part will work reliably in your application.

Thanks,

John