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TPS65217: SYS voltage Issue

Sachith Eranna
Prodigy 20 points
Part Number: TPS65217

Hi,

Currently we are testing the TPS65217D PMIC in one of the project.we have followed the design of Beagle bone black schematic we are providing the 5V through USB pin.

we are getting the bypass voltage of 2.25v and INTLDO of 2.3V but the SYS pin is output is stuck at 1.1V.

Can you please suggest the solution.As we have tried the TPS65217 checklist and still problem persists

Regards,
Sachith

  • 0
    TI__Mastermind 19530 points

    Hi Sachith,

    • Can you send me your schematic and layout files as PDF documents so that I have them for reference? (PDF helps me search for net names and components)
    • Can you provide the following scope captures? Please label the waveforms and include multiple signals per capture so I can compare the timings on the rising edges. Also specify the time and voltage divisions used.
      • rising edges of VUSB, VSYS, nWAKEUP, and PWR_EN
      • rising edges of VSYS, LDO1, DCDC1, and LDO3

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 20 points

    Hi I have shared the measured oscilloscope image for VRTC - 1.8V and suddenly it is dropping of to 0v and in 2nd image VSYS is coming 5v and then dropping of to 1.1v constantly.

    Due to some restrictions I am not having rights to share the schematic files

  • 0 in reply to Sachith Eranna
    TI__Mastermind 19530 points

    Hi Sachith,

    I can set up a private message for you to share the schematic / layout files as a PDF. The files would only be shared with me to help with this issue. If this is acceptable, please accept my friend request so I can open up the private message space.

    Also are you able to provide the scope captures I mentioned in my last post? It would help if each scope capture had 4 signals so I can see the timing of the waveforms better. I can see VSYS and VLDO1 (VRTC) here but there are other signals like VUSB, nWAKEUP, and PWR_EN that I would like to see all in one scope capture.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Mastermind 19530 points

    Hi Sachith,

    I received your message, please allow me 3 business days to review the schematic and provide feedback.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Mastermind 19530 points

    Hi Sachith,

    Here are some notes on the schematic:

    • It looks like you have the VDCDC1 FB connected to a resistor divider. This resistor divider is taking your 1.35V output from DCDC1 and dropping it to 0.54V according to my calculations. The VDCDC1 FB pin is looking for 1.35V so this is likely causing the DCDC1 output to ramp up higher than normal and trigger a fault. Usually VDCDCx pins are connected directly to the output node between the inductor and capacitors. Can you check the DCDC1 output voltage waveform?

    • I'm not sure what FB13 and FB14 are used for on LS1_OUT and LS2_OUT, but these components are not part of the beagle bone schematic. It looks like they have some resistance values so if they interfere with the output voltage target I would remove them.

    • I can't see VLDO2 from the schematic picture but it should be connected to GND through a 2.2 uF capacitor.
    • Even though the beagle bone schematic does not include a 22uF capacitor on the SYS pins, I would recommend adding this capacitor to see if it improves performance.

    Regards,

    James