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TPS62816-Q1: COMP/FSET pin design

jianyan xia
Prodigy 50 points
Part Number: TPS62816-Q1

   These three descriptions in the manual are not very clear, please help to interpret them, thank you

1. When working in PWM mode, why should minimum open time and minimum close time be considered when setting frequency through COMP/FSET's resistance to the ground?Is the specification of ton and min referred to the upper tube or the lower tube?

 

2. As shown in the screenshot below, what does V represent in the formula for calculating the minimum output capacitance?Does it mean the input voltage?

3. What is the internal structure of COMP/FSET pin?In R11002 and a 10 nF capacitor, the PWM frequency at SW end is relatively stable, R11002 and a 100 nF capacitor, the PWM frequency at SW end is in variable frequency mode

  • +1
    TI__Intellectual 2040 points

    Hi, 


    Thank you for the inquiry. 

    I will address your questions as follows:

    • jianyan xia said:
      1. When working in PWM mode, why should minimum open time and minimum close time be considered when setting frequency through COMP/FSET's resistance to the ground?Is the specification of ton and min referred to the upper tube or the lower tube?

    Referring to screenshot you shared, the min on time in the calculation for fs,max is considering the min on time of the high-side FET. For more information regarding the the minimum on time and its relation to other parameters, please refer to this Application note: "Understanding output voltage limitations of DC/DC buck converters". 

    Application note: https://www.ti.com/lit/an/slyt293/slyt293.pdf?ts=1685602881812

    • jianyan xia said:
      2. As shown in the screenshot below, what does V represent in the formula for calculating the minimum output capacitance?Does it mean the input voltage?

    In the formula for minimum output capacitance, V/ Vout is a ratio where V = 1 V. For example in the highlighted equation, if Vout = 1.3 V, minimum output capacitance = 32 uF x (1 V/ 1.3 V) = 24.6 uF.

    • jianyan xia said:
      3. What is the internal structure of COMP/FSET pin?In R11002 and a 10 nF capacitor, the PWM frequency at SW end is relatively stable, R11002 and a 100 nF capacitor, the PWM frequency at SW end is in variable frequency mode

    The COMP/FSET pin is used for device compensation and frequency set input. For more information regarding its functionality, please refer to section 9.3.2 in the datasheet, titled "COMP/FSET".

    Thank you. 

    Kind Regards,
    Rameen

  • 0
    Prodigy 50 points

    Hi Rameen,

    Thank you for you reply.

    I have doubts about the third question

    • 3. What is the internal structure of COMP/FSET pin?In R11002 and a 10 nF capacitor, the PWM frequency at SW end is relatively stable, R11002 and a 100 nF capacitor, the PWM frequency at SW end is in variable frequency mode

    The COMP/FSET pin is used for device compensation and frequency set input. For more information regarding its functionality, please refer to section 9.3.2 in the datasheet, titled "COMP/FSET".

    without any description about,the structure about COMP/FSET pin,As follows

    When the ripple is tested, it is found that the ripple regularly increases/decreases, and the frequency is about 32K(both light and heavy load). When the ripple is large, the corresponding frequency of the SW signal changes greatly.

    But in pin:MODE/SYNC, I was forced to work in PWM mode, and the output of the chip was not as expected. Please help to analyze it, thank you!

    Overshoot, when the ripple is large, the frequencies of adjacent periods are 2.53M and 1.89M, respectively

    Undershoot, when the ripple is large, the frequencies of adjacent periods are 1.82M and 1.52M, respectively

  • 0
    TI__Intellectual 2040 points

    Hi, 

    Thank you for the inquiry.

    jianyan xia said:
    When the ripple is tested, it is found that the ripple regularly increases/decreases, and the frequency is about 32K(both light and heavy load). When the ripple is large, the corresponding frequency of the SW signal changes greatly.

    I need the complete information to be able to provide proper recommendations. 
    Could you let me know about the parameters you are using? 
    What is the COMP setting that you are using in the circuit? 
    Have you connected the MODE/SYNC to high or low? 
    Additionally, where are you measuring the output voltage?

    Please refer to table 9-1 in the datasheet for the appropriate COMP setting according to the output capacitance used in the circuit. 
    Moreover, it would also help if I could review your schematic. 

    Thank you. 

    Kind Regards,
    Rameen

  • 0
    Prodigy 50 points

    Hi Rameen,

    Thank you for you reply.

    What is the COMP setting that you are using in the circuit? 

    ：connect 100k resister to ground,reference the fellowing picture
    Have you connected the MODE/SYNC to high or low? 

    ：pull high,connect 4.7k resister to Vin,reference the fellowing picture
    Additionally, where are you measuring the output voltage?

    ：the buck output capacitor,reference the fellowing picture

    Please refer to table 9-1 in the datasheet for the appropriate COMP setting according to the output capacitance used in the circuit. 
    Moreover, it would also help if I could review your schematic. 

  • 0
    TI__Intellectual 2040 points

    Hi, 

    Thank you for sharing the schematic. I don't see any issues there. 

    jianyan xia said:

    Please refer to table 9-1 in the datasheet for the appropriate COMP setting according to the output capacitance used in the circuit. 
    Moreover, it would also help if I could review your schematic. 

    Would it be possible to check the layout as well? Perhaps, I can identify an issue in the layout that may be causing the frequency variations?

    Thank you.

    Kind Regards, 

    Rameen

  • 0
    Prodigy 50 points

    Hi Rameen,

    Thank you for you reply.

    layout for you

  • 0
    TI__Intellectual 2040 points

    Hi,

    Thanks for sharing the layout. 

    Could you explain how the Mode pin (Pin 1) is connected? 

    Additionally, Could you also provide some background on how the switching frequency was measured? Also, where it was measured? At the switch node? 

    jianyan xia said:
    layout for you

    Additionally, I would recommend checking out this video which provides tips on measuring Vout ripple and switching frequency. 

    https://www.ti.com/video/5779650185001

    Thank you. 

    Kind Regards,
    Rameen

  • 0
    Prodigy 50 points

    Hi Rameen,

    Thank you for you reply.

    1.pin 1 trace is for the yellow line

    2.test point as bellow,test through Passive probe,at the switch mode, Use the same method to test other BUCK switch frequency

  • 0
    TI__Intellectual 2040 points

    Hi, 

    I would suggest to try measuring the frequency directly at the switch node.

    There doesn't seem to be an issue in your layout or schematic. So perhaps, it is a matter on how the frequency is measured. 

    jianyan xia said:
    2.test point as bellow,test through Passive probe,at the switch mode, Use the same method to test other BUCK switch frequency

    Thank you.

    Kind Regards,

    Rameen

  • 0
    Prodigy 50 points

    Hi 

     this test point is at the switch node.

    Corresponding position in the SCH

  • 0
    Prodigy 50 points

    Hi

    The frequency vibrate, maybe caused by the buck chip ?

  • 0
    TI__Intellectual 2040 points

    Hi,

    jianyan xia said:
    The frequency vibrate, maybe caused by the buck chip ?

    Since your schematic was properly configured and the components connected appropriately in the layout, I do not see how the converter could have caused it. 
    We have not seen any such issue in the converter from our side. 

    Thank you.

    Kind Regards,

    Rameen