LMG1025-Q1EVM: About the setting of function generator

Hello Hidenobu-san,

I also checked, and with 5V on the AND gate device, it does look like it should not respond to a 3V signal. That must be an oversight, and a 5V signal from the FG will be necessary. 

As for the other questions in the attached document:

1. Could you tell me the condition of Rise/Fall times of function generator?

Ideally, the rise/fall time should be as fast as possible, and then the pulse shortening can be easily controlled with the AND gate. There are two limitations, one is the dv/dt rating of the AND gate device. I can only see the minimum in the datasheet, and the max is most likely unattainable with a normal setup. The other is the rise/fall time that can actually be achieved in the system. I would recommend picking a device you plan to use for the input in an actual system, determining its rise and fall time in this condition, and mimicking it with the FG. Otherwise, just set the rise and fall time as low as the FG supports.

2. Do you use the below condition of RC filter to generate 1ns pulse?

Assuming you mean the RC values, then yes. There is some uncertainty and variability in the RC values and the AND gate's threshold. This is why the procedure suggests to achieve the pulse by shortening the input rather than changing RC values. There is no reason why different values could not be used though. 

Thanks,

Alex M.

Hello Hidenobu-san,

1. Did you measure FWHM of peak when you evaluated the pulse width(In+, Vg, and other pulse)?

The document is referencing the width measurement given by the scope. My understanding is that this scope gives its width measurements in terms of 50% thresholds of the pulse- basically FWHM.

2. If generating short pulse, are the pulse width and peak quite variable?(Is that stable?)

I don't know a good metric for this. In my experience, the driver should output the same pulse when given the same input, as long as VDD and temperature stay constant (sometimes the driver can heat significantly when switching fast). I do not know as much about the performance of the pulse buffer circuit. I think the best method would be to measure these captures in persistence mode on your scope to evaluate the jitter/variability.

3. Is the pulse width of Vr shorter than In+ and Vg?

It depends on the FET, Vbus, and resistance. In general, Vg should be about ~300ps longer than IN due to pulse width distortion. In this capture, the distortion was low, but you can see more in other captures in the datasheet. Rise and fall times due to Qg can cause different behavior though.

The VDS width is determined by gate voltage, ID current, and Cds capacitance. VDS + VR should be equal to the bus voltage due to KVL. It looks like it isn't adding up, which may be due to unmeasured parasitics. Basically, your Vr looks more narrow than Vg, but it depends on the characteristics of the FET and resistive load.

Thanks,

Alex M.