CSD13381F4: When upper FET is off, i have a VGS of -0.6V

guy lemire

Part Number: CSD13381F4
Other Parts Discussed in Thread: CSD, CSD17382F4, CSD13383F4

Hello,

I am using the CSD in the below circuit. the circuit opertes with either one of the FETs on or both off.

However when I have the upper FET disabled (0V applied to gate), I have an effective Vgs voltage of about -0.6V. There is a protection diode between the gate and source which i think is being turned on as i am seeing leakage current which is effecting my bias point VDDQ_trim which is at 0.6V. Is there an alternative circuit which would allow me to enable /disable the top fet without the diode being at least partially forward biased or is there an alternative fet that you could recommend to use.

over 1 year ago

0 John Wallace1 over 1 year ago

TI__Mastermind 32405 points

Hello Guy,

Thanks for your interest in TI FETs. If the source (VDDQ_TRIM) of U30 is higher than its gate (VDDQ_MARGIN_DOWN) then you are forward biasing the single-ended gate ESD protection diode. We have two alternatives, CSD17382F4 and CSD13383F4, in the same package that use a back-to-back ESD structure that will prevent this from happening. The back-to-back structure results in higher leakage (IGSS and IDSS) and the 1k price is slightly higher for these devices. The link below explains the ESD protection used in TI FETs.

https://e2e.ti.com/blogs_/b/powerhouse/posts/what-type-of-esd-protection-does-your-mosfet-include

Best Regards,

John Wallace

TI FET Applications

0 guy lemire over 1 year ago in reply to John Wallace1

Intellectual 950 points

Hi John,

thank you for your excellent response. This solved my issue. Please close this case.

Regards,

Guy

Power management

Power management forum

CSD13381F4: When upper FET is off, i have a VGS of -0.6V