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CSD13381F4: When upper FET is off, i have a VGS of -0.6V

Part Number: CSD13381F4
Other Parts Discussed in Thread: CSD, CSD17382F4, CSD13383F4


I am using the CSD in the below circuit. the circuit opertes with either one of the FETs on or both off.

However when I have the upper FET disabled (0V applied to gate), I have an effective Vgs voltage of about -0.6V. There is a protection diode between the gate and source which i think is being turned on as i am seeing leakage current which is effecting my bias point VDDQ_trim which is at 0.6V. Is there an alternative circuit which would allow me to enable /disable the top fet without the diode being at least partially forward biased or is there an alternative fet that you could recommend to use.