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BQ25898: About CHRG_FAULT register

Part Number: BQ25898
Other Parts Discussed in Thread: TIGER

Hi.

Could you tell me about CHRG_FAULT?

1. Is CHRG_FAULT bit valid even when CHRG_STAT bit is not charging status?
 If ”VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V)” is satisfied,
      does CHRG_FAULT bit become input fault even when not charging condition?

2. If 1 is Yes, How long is the deglitch time from detecting an input fault to switching the CHRG_FAULT bit?
   
 Customer has confirmed that CHRG_STAT is 01 (input fault) even when CHRG_STAT is 00 (not charging) when removing the USB.
    I am asking this question in that background.

Best regards,
Yusuke

  • Hi Yusuke, 

    Please see my comments below. 

    1) Yes, even when CHRG_STAT is 00 (not charging) CHRG_FAULT can read 01 to indicate an input fault. 

    Customer has confirmed that CHRG_STAT is 01 (input fault) even when CHRG_STAT is 00 (not charging) when removing the USB.
        I am asking this question in that background.

    I do not see this behavior when testing on BQ25898EVM. With the device not charging I see CHRG_FAULT = 01 to indicate when VBUS voltage > VACOV, or when VBAT < VBUS < VVbusmin matching the datasheet description. If input USB is fully removed I do not observe CHRG_FAULT = 01 (input fault). 

    Please advise the customer to double check their experiment. One theory is if in their test setup VBUS voltage slowly decays after USB is removed there may be a short timeframe where VBAT < VBUS < VVBUSMIN condition is valid. 

    Best Regards,

    Garrett 

  • Hi Garrett,

    Thank you for your response.
    >Please advise the customer to double check their experiment. One theory is if in their test setup VBUS voltage slowly decays after USB is removed there >may be a short timeframe where VBAT < VBUS < VVBUSMIN condition is valid. 
    It takes about 40msec for the VBUS voltage to transition from 3.84V to 3.36V.
    Is this time a problem?

    And I got a test waveform from a customer.
    Could you send it by private message?

    >2. If 1 is Yes, How long is the deglitch time from detecting an input fault to switching the CHRG_FAULT bit?
    Do you have any information about the above question related to "VBUS voltage slowly decays after USB is removed"?

    When an input fault occurs, an error UI is displayed on the customer set side.
    Therefore, the customer wants to know how much the VBUS falling slew rate can be avoided.

    Best regards,
    Yusuke

  • Hi Yusuke, 

    I sent you a private message on E2E. Please help to provide the customer waveform. I will need to review before I can comment further on item 2 regarding timing to detect and report an input fault. 

    It takes about 40msec for the VBUS voltage to transition from 3.84V to 3.36V.
    Is this time a problem?

    From the perspective of the BQ25898 the time for VBUS to decay is not a problem, but it likely explains why customer observes an input fault at CHG_FAULT status register. 

    Best Regards, 

    Garrett 

  • Hi Garrett,

    Thank you for your support.
    I sent you a private message.
    We kindly ask for your confirmation.

    Regards,
    Yusuke

  • Hi Yusuke, 

    I have received the waveforms. We are looking into them further and will get back to you. Thank you for your patience. 

    Best Regards,

    Garrett 

  • Hi Garrett,

    Thank you for your response.
    We look forward to hearing back from you. 

    Best Regards,
    Yusuke

  • Hi Yusuke, 

    Please see my comments below regarding question 2. 

    Based on the waveform capture showing 2 interrupts I believe the 1st interrupt is generated due to device detecting input removal. Then the 2nd interrupt is generated in response to the input fault being detected. The CHRG_FAULT bit is set at the same time the 2nd interrupt is generated. 

    Based on this timing it appears the device takes approx. 40msec to detect that VBUS is < VBUSMIN and > VBAT then set the CHARGE_FAULT bits.

    The best solution to avoid the error UI would be to add a resistor at VBUS to speed up the voltage decay when USB is removed. An alternative option would be to make a firmware adjustment to ignore input fault when it occurs directly following input removal. 

    Best Regards,

    Garrett 

  • Hi Garrett,

    Thank you for your support.
    >The best solution to avoid the error UI would be to add a resistor at VBUS to speed up the voltage decay when USB is removed. An alternative option would >be to make a firmware adjustment to ignore input fault when it occurs directly following input removal. 

    I will announce the above measures to the customer.
    However, we need an indication of the VBUS ramp-down speed for the following discussion.
    >The best solution to avoid the error UI would be to add a resistor at VBUS to speed up the voltage decay when USB is removed.

    What should be the VBUS falling slew rate?
    Or How long is the deglitch time from detecting an input fault to switching the CHRG_FAULT bit?

    Best Regards,
    Yusuke

  • The team is currently on holiday break. Please wait for a response later.

  • Hi Tiger,

    Thank you for your response.
    >The team is currently on holiday break.
    I understand the reason for your post.

    I got feedback and additional questions from customers.
    I will list it below.

    >An alternative option would be to make a firmware adjustment to ignore input fault when it occurs directly following input removal. 

    When masked by firmware, USB removal and input voltage fault cannot be distinguished.
    Any advice on how to separate a USB disconnection from a true input voltage fault?
    Customer concerned about masking an input voltage fault when it occurs and ignoring it in the process.

    >The best solution to avoid the error UI would be to add a resistor at VBUS to speed up the voltage decay when USB is removed.
    Customer wants to know the VBUS fall time criteria for USB remove interrupt and input fault interrupt isolation.
    Could you tell me again about the VBUS voltage drop slew rate or the detection time?

    Best Regards,
    Yusuke

  • Hi Yusuke, 

    Unfortunately, I have not been able to verify the exact deglitch timing for the device to detect an input fault. Also note the required VBUS drop slew rate will change depending on the BAT voltage. Input fault is triggered when VBUS is < 3.8V, but still > VBAT. Therefore, for example if BAT is fully charged at 4.2V an input fault should not occur when USB is disconnected. 

    Please see my comments below in regards to the additional question. 

    Any advice on how to separate a USB disconnection from a true input voltage fault?

    The best way to separate a true input fault from a USB disconnection may be to read the fault register multiple times before outputting the error UI. For a true input fault the fault status will remain set on REG0C, whereas if it is just a USB disconnection the fault will no longer be present on the 2nd read of REG0C. 

    Best Regards,

    Garrett 

  • Hi Garrett,

    Thank you for your kind support.
    I got a question about CHRG_FAULT related to this issue.

    1.
    For example, if the VBUS voltage drops slightly during charging operation and "CHRG_FAULT" becomes 01 (Input fault),when the VBUS voltage returns to normal, CHRG_FAULT automatically returns to 00 (Normal) for charging.
    Is this understanding correct?

    2.
    If CHRG_FAULT returns to 00 (Normal),
    How long after VBUS returns to normal voltage does CHRG_FAULT return to 00 (Normal)?

    3.
    CHRG_FAULT becomes 01 (Input fault) when the USB is removed, will this 01 (Input fault) automatically return to 00 (Normal)?
    If CHRG_FAULT returns to 00 (Normal),How long does it take to return to 00 after removing VBUS?

    Best Regards,
    Yusuke

  • Hi Yusuke, 

    Please see my comments below. 

    1) Yes CHRG_FAULT will return to 00 when VBUS returns to normal, but the customer will need to read REG0C twice in a row to see current status. Section 9.2.9.2 of the BQ25898 datasheet on page 27 explains how REG0C remains in the fault state until the host reads the register. Therefore to see the current fault status after a fault has occurred I2C host must read REG0C two times consecutively. 

    2) We are not able to provide exact deglitch timing on this. When the device detects VBUS return to normal voltage or drop below VBAT CHRG_FAULT status will immediately be set back to 00b.  

    3)See 1) for explanation of REG0C needing to be read twice to return to 00b.  

    Regards,

    Garrett