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TLC5923: Tpd Duration

Vered Karp
Prodigy 30 points
Part Number: TLC5923

Hi,

I have TLC5923 in my design and I'm trying to understand the Tpd between clock and Sout.
According to datasheet, the maximal clock frequency is 30MHz, i.e. the pulse width is 33ns, while the Tpd is 30ns.
It looks like the Tpd is very close to the pulse width. It means that if for example I need to add a level shifter between TLC5923 and the FPGA the Tpd of the level shifter should be about 1.5ns which is very small Tpd. Am I right? If not, can you please explain what am I missing?

Thanks,
Vered

  • 0
    TI__Expert 6440 points

    Hi,

    30Mhz is the maximum value for clock frequency, and 30ns is the maximum value for Tpd.

    You can use lower clock frequency so that the pulse width will be longer than Tpd.

    I don't think you need to add a level shifter between TLC5923 and FPGA.

    Thanks!

  • 0
    Prodigy 30 points

    Hi,

    Just to make sure I understood clear:

    1. is it not necessary that Sout will have a valid value before the next clock cycle?
    2. If so, how does TLC5923 relate Sout to the right Sin, and not to the next Sin?
    3. If it is necessary that Sout will have a valid value before the next clock cycle, why is it valid that Tpd is greater than the time of a clock cycle (for adding a level shifter for example)?

    Thanks in advance,
    Vered

  • 0 in reply to Vered Karp
    TI__Expert 6440 points

    Hi,

    Sout will be prepared to the right state before SCLK rising edge, only in this way the right signal could be input to next device.

    And this process is achieved by internal circuit, and it is not easy to describe. 

    And the 30ns Tpd is the maximum value, and it can be less than 30ns in real applications.

    If the SOUT could on the right state before next rising edge of SCLK, it can work properly.

    Like you mentioned, the pulse width of SCLK is 33ns, and Tpd's maximum value is 30ns, so the period between 2 SCLK rising edge is 33ns, and is larger than 30ns Tpd, so SOUT could be prepared before next SCLK.

    Thanks!