Hello,
Is the KVFF value or the equation (13) of IIMO in the data sheet different between single- and three-phase inputs? These are the operating conditions of the circuit.
Besides, which KVFF value must be chosen if the levels of VINAC and VIN are different in Table 1?
Best regards,
Shinichi Yokota
Hi Shinichi-San,
Thank you for the query on UCC28070.
The UCC28070 is designed for single phase applications only. There is no separate Kvff table for 3 phase case.
So for single phase case since your input voltage range is from 254Vpk to 311Vpk, so Imo and Kvff will be selected as below:
I am attaching a document on the recommended approach for 3phase PFCs using UCC28070.
6558.Designing with 3 phase PFCs.doc
One risk is that the ripple will in VINAC be too small to perform the Vff update in a three phase application where Kvff update requires this signal to be below 0.7V for 50us for zero crossing detection inside the controller. This will update Kvff as your input voltage changes and it relies on this zero crossing dtection. The reason for this is elaborated in figure -2 of the document and result is it will not result in proper phase currents and THD will be higher, and the lack of zero-crossings at VINAC will cause the controller to be stuck at a low gain.
Figure 4 arrangement has an independent 1-phase PFC for each pair of lines of the 3-phase input line. Each will work properly at 1/3 of the total power requirement. However, due to the input rectification, + and - rail voltages are not the same; they are out of phase with each other and the PFC outputs CANNOT be directly connected together. Each requires an isolating conversion stage first, to isolate the outputs from the inputs. After the downstream converters, their output grounds CAN be connected together and the total output applied to a common load.
Please let us know if you have further questions.
Regards,
Harish
Harish,
Thanks for your support. I have three additional questions.
One risk is that the ripple will in VINAC be too small to perform the Vff update in a three phase application where Kvff update requires this signal to be below 0.7V for 50us for zero crossing detection inside the controller.
Best regards,
Shinichi Yokota
Hi Shinichi-San,
Thank you for the reply.
1. It is going to be difficult to implement as this method has not been tested or proved at TI. But I can give an outline of the process which has been suggested by experts here as a workaround. The VINAC pin was designed for very low switching frequency 40 to 200Hz and requires dv/dt in the range of 1-4mv/us for kvff update.
Proposal would be to use a notch circuit, where a 555 timer is used to generate 50hz sinal synchronized with the zero crossing of AC voltage waveform. The MOSFET will discharge the VINAC capacitor and the resistance in series is used to adjust dv/dt optimal for Kvff update.
2. Kvff update takes place according to the peak values as shown in table -1. Without proper Kvff update the converter will be power limited as without zero-crossing signal, Kvff keeps level 8 when input is DC voltage. So if there is not sufficient zero crossing to detect level change customer would need to implement something similar to above or consider implementing three single phase PFC across each of the phases as suggested in the previous document.
3. You can try something like below using bleeder resistors.
Thank you
Regards,
Harish
Harish,
Please let me rephrase the question No.2.
In a previous answer of this thread, you selected 1.65 V for the parameter VVINAC of the Equation 13 for the single-phase input voltage range from 180 to 220 V (254 to 311 Vpk), and I was wondering where the 1.65 V comes from.
Since the KVFF value is 1.604 V2, I thought that the Level in the Table 1 of the data sheet is 5 in this case and eventually 1.65 V was chosen from the Level 5.
Then, my question No.2 comes. I suspect that the lowest VVINAC peak voltage should be chosen for a selected Level for the Equation 13 such as 1 VVINAC(pk) for the Level 2, 1.2 VVINAC(pk) for the Level 3, and forth from the Table 1, but is my understanding correct?
Table 1
Best regards,
Shinichi Yokota
